Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Published on 23. October 2014
Book
Paperback/Softback
XXII, 170 pages
978-1-4899-8780-8 (ISBN)
Description
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
More details
Edition
2012 ed.
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XXII, 170 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 11 mm
Weight
300 gr
ISBN-13
978-1-4899-8780-8 (9781489987808)
DOI
10.1007/978-1-4614-0872-7
Schweitzer Classification
Other editions
Additional editions
Sumit Ahuja | Avinash Lakshminarayana | Sandeep Kumar Shukla
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
E-Book
10/2011
1st Edition
Springer
€96.29
Available for download
Sumit Ahuja | Avinash Lakshminarayana | Sandeep Kumar Shukla
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Book
10/2011
Springer
€106.99
Shipment within 15-20 days
Content
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.