Electronic Design Automation
Synthesis, Verification, and Test
Published on 26. March 2009
Book
Hardback
972 pages
978-0-12-374364-0 (ISBN)
Description
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
More details
Series
Language
English
Place of publication
San Francisco
United States
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
Practitioners/Researchers in electronic design automation, including VLSI design engineers, verfication engineers, and test engineers.
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 287 mm
Width: 222 mm
Thickness: 55 mm
Weight
2841 gr
ISBN-13
978-0-12-374364-0 (9780123743640)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Laung-Terng Wang | Yao-Wen Chang | Kwang-Ting (Tim) Cheng
Electronic Design Automation
Synthesis, Verification, and Test
E-Book
03/2009
Morgan Kaufmann
€73.95
Available for download
Persons
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007). Yao-Wen Chang, Ph.D., is a Professor in the Department of Electrical Engineering, National Taiwan University. He recevied his Ph.D. degree in Computer Science from the University of Texas at Austin. He has published over 200 technical papers, co-authored one book, and is a winner of the ACM ISPD Placement (2006) and Global Routing (2008) contests. Kwang-Ting (Tim) Cheng, Ph.D., is a Professor and Chair of the Electrical and Computer Engineering Department at the University of California, Berkeley. A Fellow of the IEEE, he has published over 300 technical papers, co-authored three books, and holds 11 U.S. Patents.
Content
Chapter 1: Introduction
Chapter 2: Fundamentals of CMOS Design
Chapter 3: Design for Testability
Chapter 4: Fundamentals of Algorithms
Chapter 5: Electronic System-Level Design and High-Level Synthesis
Chapter 6: Logic Synthesis in a Nutshell
Chapter 7: Test Synthesis
Chapter 8: Logic and Circuit Simulation
Chapter 9: Functional Verification
Chapter 10: Floorplanning
Chapter 11: Placement
Chapter 12: Global and Detailed Routing
Chapter 13: Synthesis of Clock and Power/Ground Networks
Chapter 14: Fault Simulation and Test Generation.
Chapter 2: Fundamentals of CMOS Design
Chapter 3: Design for Testability
Chapter 4: Fundamentals of Algorithms
Chapter 5: Electronic System-Level Design and High-Level Synthesis
Chapter 6: Logic Synthesis in a Nutshell
Chapter 7: Test Synthesis
Chapter 8: Logic and Circuit Simulation
Chapter 9: Functional Verification
Chapter 10: Floorplanning
Chapter 11: Placement
Chapter 12: Global and Detailed Routing
Chapter 13: Synthesis of Clock and Power/Ground Networks
Chapter 14: Fault Simulation and Test Generation.