CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Process-Aware SRAM Design and Test
Published on 21. June 2008
Book
Hardback
XVI, 194 pages
978-1-4020-8362-4 (ISBN)
Description
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
More details
Series
Edition
2008 ed.
Language
English
Place of publication
Dordrecht
Netherlands
Target group
Professional and scholarly
Research
Product notice
sewn/stitched
Cloth over boards
Illustrations
XVI, 194 p.
Dimensions
Height: 242 mm
Width: 166 mm
Thickness: 19 mm
Weight
445 gr
ISBN-13
978-1-4020-8362-4 (9781402083624)
DOI
10.1007/978-1-4020-8363-1
Schweitzer Classification
Other editions
Additional editions
Andrei Pavlov | Manoj Sachdev
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Process-Aware SRAM Design and Test
Book
10/2010
Springer
€171.19
Shipment within 15-20 days
Andrei Pavlov | Manoj Sachdev
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Process-Aware SRAM Design and Test
E-Book
06/2008
1st Edition
Springer
€160.49
Available for download
Persons
Prof. Sachdev has authored several successful books with Springer
Content
and Motivation.- SRAM Circuit Design and Operation.- SRAM Cell Stability: Definition, Modeling and Testing.- Traditional SRAM Fault Models and Test Practices.- Techniques for Detection of SRAM Cells with Stability Faults.- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.