Gan Transistors for Efficient Power Conversion

Foreword Acknowledgments 1 GaN Technology Overview 1.1 Silicon Power MOSFETs 1976-2010 1.2 The GaN Journey Begins 1.3 Gallium Nitride and Silicon Carbide Compared with Silicon 1.3.1 Band Gap (Eg) 1.3.2 Critical Field (Ecrit) 1.3.3 On-Resistance (RDS(on)) 1.3.4 The Two-Dimensional Electron Gas 1.4 The Basic GaN Transistor Structure 1.4.1 Recessed Gate Enhancement-Mode Structure 1.4.2 Implanted Gate Enhancement-Mode Structure 1.4.3 pGaN Gate Enhancement-Mode Structure 1.4.4 Hybrid Normally-Off Structures 1.4.5 Reverse Conduction in HEMT Transistors 1.5 Building a GaN Transistor 1.5.1 Substrate Material Selection 1.5.2 Growing the Heteroepitaxy 1.5.3 Processing the Wafer 1.5.4 Making Electrical Connection to the Outside World 1.6 GaN Integrated Circuits 1.7 Summary References 2 GaN Transistor Electrical Characteristics 2.1 Introduction 2.2 Device Ratings 2.2.1 Drain-Source Voltage 2.3 On-Resistance (RDS(on)) 2.4 Threshold Voltage 2.5 Capacitance and Charge 2.6 Reverse Conduction 2.7 Summary References 3 Driving GaN Transistors 3.1 Introduction 3.2 Gate Drive Voltage 3.3 Gate Drive Resistance 3.4 Capacitive Current-Mode Gate Drive Circuits for Gate Injection Transistors (GIT) 3.5 dv/dt Considerations 3.5.1 Controlling dv/dt at Turn-On 3.5.2 Complimentary Device Turn-On 3.6 di/dt Considerations 3.6.1 Device Turn-On and Common Source Inductance 3.6.2 Off-State Device di/dt 3.7 Bootstrapping and Floating Supplies 3.8 Transient Immunity 3.9 High Frequency Considerations 3.10 Gate Drivers for Enhancement-Mode GaN 3.11 Cascode, Direct Drive, and Higher Voltage Configurations 3.11.1 Cascode Devices 3.11.2 Direct Drive Devices 3.11.3 Higher Voltage Configurations 3.12 Summary References 4 Layout Considerations for GaN Transistor Circuits 4.1 Introduction 4.2 Minimizing Parasitic Inductances 4.3 Conventional Power Loop Designs 4.3.1 Lateral Power Loop Design 4.3.2 Vertical Power Loop Design 4.4 Optimizing the Power Loop 4.4.1 Impact of Integration on Parasitics 4.5 Paralleling GaN Transistors 4.5.1 Paralleling GaN Transistors for a Single Switch 4.5.2 Paralleling GaN Transistors for Half-Bridge Applications 4.6 Summary References 5 Modeling, Simulation, and Measurement of GaN Transistors 5.1 Introduction 5.2 Electrical Modeling 5.2.1 Basic Modeling 5.2.2 Limitations of Basic Modeling 5.2.3 Limitations of Circuit Simulation 5.3 Measuring GaN Transistor Performance 5.3.1 Voltage Measurement Requirements 5.3.2 Probing and Measurement Techniques 5.3.3 Measuring Non-Ground-Referenced Signals 5.3.4 Current Measurement Requirement 5.4 Summary References 6 Thermal Management 6.1 Introduction 6.2 Thermal Equivalent Circuits 6.2.1 Thermal Resistance in a Lead-Frame Package 6.2.2 Thermal Resistance in a Chip-Scale Package 6.2.3 Junction-to-Ambient Thermal Resistance 6.2.4 Transient Thermal Impedance 6.3 Improving Thermal Performance with a Heatsink 6.3.1 Selection of Heatsink and Thermal Interface Material 6.3.2 Heatsink Attachment for Bottom-Side Cooling 6.3.3 Heatsink Attachment for Multi-Sided Cooling 6.4 System-Level Thermal Analysis 6.4.1 Thermal Model of a Power Stage with Discrete GaN Transistors 6.4.2 Thermal Model of a Power Stage with a Monolithic GaN Integrated Circuit 6.4.3 Thermal Model of a Multi-Phase System 6.4.4 Temperature Measurement 6.4.5 Experimental Characterization 6.4.6 Application Examples 6.5 Summary References 7 Hard-Switching Topologies 7.1 Introduction 7.2 Hard-Switching Loss Analysis 7.2.1 Hard Switching Transitions with GaN Transistors 7.2.2 Output Capacitance (COSS) Losses 7.2.3 Turn-On Overlap Loss 7.2.3.1 Current Rise Time 7.2.3.2 Voltage Fall Time 7.2.4 Turn-Off Overlap Losses 7.2.4.1 Current Fall Time 7.2.4.2 Voltage Rise Time 7.2.5 Gate Charge (QG) Losses 7.2.6 Reverse Conduction Losses (PSD) 7.2.6.1 Impact of Dead-Time Selection on Reverse Conduction Loss 7.2.6.2 Adding an Anti-Parallel Schottky Diode 7.2.6.3 Dynamic COSS-Related Reverse Conduction Losses 7.2.7 Reverse Recovery (QRR) Losses 7.2.8 Hard-Switching Figure of Merit 7.3 Impact of Parasitic Inductance on Hard-Switching Losses 7.3.1 Impact of Common-Source Inductance (LCS) 7.3.2 Impact of Power Loop Inductance on Device Losses 7.4 Frequency Impact on Magnetics 7.4.1 Transformers 7.4.2 Inductors 7.5 Buck Converter Example 7.5.1 Comparison with Experimental Measurements 7.5.2 Consideration of Parasitic Inductance 7.6 Summary References 8 Resonant and Soft-Switching Converters 8.1 Introduction 8.2 Resonant and Soft-Switching Techniques 8.2.1 Zero-Voltage and Zero-Current Switching 8.2.2 Resonant DC-DC Converters 8.2.3 Resonant Network Combinations 8.2.4 Resonant Network Operating Principles 8.2.5 Resonant Switching Cells 8.2.6 Soft-Switching DC-DC Converters 8.3 Key Device Parameters for Resonant and Soft-Switching Applications 8.3.1 Output Charge (QOSS) 8.3.2 Determining Output Charge from Manufacturers' Datasheet 8.3.3 Comparing Output Charge of GaN Transistors and Si MOSFETs 8.3.4 Gate Charge (QG) 8.3.5 Determining Gate Charge for Resonant and Soft-Switching Applications 8.3.6 Comparing Gate Charge of GaN Transistors and Si MOSFETs 8.3.7 Comparing Performance Metrics of GaN Transistors and Si MOSFETs 8.4 High-Frequency Resonant Bus Converter Example 8.4.1 Resonant GaN and Si Bus Converter Designs 8.4.2 GaN and Si Device Comparison 8.4.3 Zero-Voltage Switching Transition 8.4.4 Efficiency and Power Loss Comparison 8.4.5 Impact of Further Device Improvements on Performance 8.5 Summary References 9 RF Performance 9.1 Introduction 9.2 Differences Between RF and Switching Transistors 9.3 RF Basics 9.4 RF Transistor Metrics 9.4.1 Determining the High-Frequency Characteristics of RF Transistors 9.4.2 Pulse Testing for Thermal Considerations 9.4.3 Analyzing the S-Parameters 9.4.3.1 Test for Stability 9.4.3.2 Transistor Input and Output Reflection 9.4.3.3 Transducer Gain 9.4.3.4 Unilateral/Bilateral Transistor Test 9.5 Amplifier Design Using Small-Signal S-Parameters 9.5.1 Conditionally Stable Bilateral Transistor Amplifier Design 9.5.1.1 Available Gain 9.5.1.2 Constant Available Gain Circles 9.6 Amplifier Design Example 9.6.1 Matching and Bias Tee Network Design 9.6.2 Experimental Verification 9.7 Summary References 10 DC-DC Power Conversion 10.1 Introduction 10.2 Non-Isolated DC-DC Converters 10.2.1 12 VIN - 1.2 VOUT Buck Converter with Discrete Devices 10.2.2 12 VIN - 1 VOUT Monolithic Half-Bridge IC Based Point-of-Load Module 10.2.3 Very High Frequency 12 VIN Monolithic Half-Bridge IC Based Point-of-Load Module 10.2.4 28 VIN - 3.3 VOUT Point-of-Load Module 10.2.5 48 VIN - 12 VOUT Buck Converter with Parallel GaN Transistors for High-Current Applications 10.3 Transformer-Based DC-DC Converters 10.3.1 Eighth-Brick Converter Example 10.3.2 High Performance 48 V Step Down LLC DC Transformer 10.3.2.1 Circuit Overview 10.3.2.2 GaN Transistor Advantage in the LLC Converter 10.3.2.3 A 1MHz, 900 W, 48 V to 12 V LLC Example Using GaN Transistors 10.3.2.4 A 1MHz, 900 W, 48 V to 6 V LLC Example Using GaN Transistors 10.4 Summary References 11 Multilevel Converters 11.1 Introduction 11.2 Benefits of Multilevel Converters 11.2.1 Applying Multilevel Converters to 48 V Applications 11.2.2 Multilevel Converters for High Voltage (400 V) Applications 11.3 Gate Driver Implementation 11.4 Bootstrap Power Supply Solutions for GaN Transistors 11.5 Multilevel Converters for PFC Applications 11.6 Experimental Examples 11.6.1 Low Voltage 11.6.2 High Voltage 11.7 Summary References 12 Class D Audio 12.1 Introduction 12.1.1 Total Harmonic Distortion 12.1.2 Intermodulation Distortion 12.2 GaN Transistor Class D Audio Amplifier Example 12.2.1 Closed-Loop Amplifier 12.2.2 Open-Loop Amplifier 12.3 Summary References 13 Lidar 13.1 Introduction to Light Detection and Ranging (Lidar) 13.2 Pulsed Laser Driver Overview 13.2.1 Pulse Requirements 13.2.2 Semiconductor Optical Sources 13.2.3 Basic Driver Circuits 13.2.4 Driver Switch Properties 13.3 Basic Design Process 13.3.1 Resonant Capacitive Discharge Laser Driver Design 13.3.2 Quantitative Effect of Stray Inductance 13.4 Hardware Driver Design 13.5 Experimental Results 13.5.1 High Speed Laser Driver Design Example 13.5.2 Fastest 13.5.3 Highest Current 13.5.4 Low Voltage 13.6 Other Considerations 13.6.1 Resonant Capacitors 13.6.2 Charging 13.6.3 Voltage Probing 13.6.4 Current Sensing 13.6.5 Dual Edge Control 13.7 Summary References 14 Envelope Tracking 14.1 Introduction 14.2 High Frequency GaN Transistors 14.3 Topologies for Envelope Tracking Supplies 14.4 Gate Driver Design 14.5 Design Example: Tracking a 20 MHz LTE Envelope Signal 14.6 Summary References 15 Wireless Power 15.1 Introduction 15.2 Overview of A Wireless Power System 15.3 Amplifiers for Wireless Power Systems 15.3.1 The Class E Amplifier 15.3.2 ZVS Class D Amplifier 15.4 Transistors Suitable for Wireless Power Amplifiers 15.4.1 Figure of Merit for Wireless Power Amplifier Topologies 15.4.2 GaN Transistor Evaluation in Wireless Power Applications 15.5 Experimental Validation of GaN Transistor Based Wireless Power Amplifiers 15.5.1 Differential-Mode Class E Amplifier Example 15.5.2 Differential-Mode ZVS Class D Amplifier Example 15.6 Summary References 16 GaN Transistors for Space Applications 16.1 Introduction 16.2 Failure Mechanisms 16.3 Standards for Radiation Exposure and Tolerance 16.4 Gamma Radiation Tolerance 16.5 Single-Event Effects (SEE) Testing 16.6 Neutron Radiation (Displacement Damage) 16.7 Performance Comparison between GaN Transistors and Rad Hard Si MOSFETs 16.8 Summary References 17 Replacing Silicon Power MOSFETs 17.1 What Controls the Rate of Adoption? 17.2 New Capabilities Enabled by GaN Transistors 17.3 GaN Transistors Are Easy to Use 17.4 Cost vs. Time 17.4.1 Starting Material 17.4.2 Epitaxial Growth 17.4.3 Wafer Fabrication 17.4.4 Test and Assembly 17.5 GaN Transistors Are Reliable 17.6 Future Direction of GaN Transistors 17.7 Summary References Appendix Index