Intel Xeon Phi Coprocessor High Performance Programming
Published on 28. March 2013
Book
Paperback/Softback
432 pages
978-0-12-410414-3 (ISBN)
Description
Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products.
This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.
This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.
Reviews / Votes
"Read this book. Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, to create this authoritative first book on the essentials of programming for this new architecture and these new products." --Slashdot.org, May 5, 2013"The authors...are uniquely experienced in software development for this new silicon. As a result, this book is the definitive programming reference for the 60+ core monster from Intel...highly readable and interlaced with lots of code examples." --DrDobbs.com, April 2, 2013
"This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come." --Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword
"The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources..." --HPCwire.com, March 31, 2013
"The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources...I got my hands on a preliminary copy of the book back in November at SC12, and I can tell you that Jim and James did a great job."--Knowledgespeak.com, April 1, 2013
More details
Language
English
Place of publication
San Francisco
United States
Publishing group
Elsevier Science & Technology
Target group
Professional and scholarly
Software engineers, High Performance and Super Computing developers, scientific researchers in need of high-performance computing resources
Dimensions
Height: 235 mm
Width: 191 mm
Weight
730 gr
ISBN-13
978-0-12-410414-3 (9780124104143)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
New editions
James Jeffers | James Reinders | Avinash Sodani
Intel Xeon Phi Processor High Performance Programming
Knights Landing Edition
Book
06/2016
2nd Edition
Morgan Kaufmann
€58.17
Article exhausted; check different version
Persons
Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel (R) MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years. James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012.
Content
1. Introduction2. High Performance examples3. Benchmarking Apps4. Real-world Situations5. Lots of Data (Vectors)6. Lots of Tasks (not Threads)7. Processing Parallelism8. Coprocessor Architecture9. Coprocessor System Software10. Linux on the Coprocessor11. Math Library12. MPI13. Profiling14. Summary