VLSI Chip Design with the Hardware Description Language VERILOG
An Introduction Based on a Large RISC Processor Design
Published on 23. August 2014
Book
Paperback/Softback
XIV, 360 pages
978-3-642-64650-8 (ISBN)
Description
The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
More details
Edition
Softcover reprint of the original 1st ed. 1996
Language
English
Place of publication
Berlin
Germany
Publishing group
Springer Berlin
Target group
Professional and scholarly
Research
Illustrations
37 s/w Abbildungen
XIV, 360 p. 37 illus.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 21 mm
Weight
569 gr
ISBN-13
978-3-642-64650-8 (9783642646508)
DOI
10.1007/978-3-642-61001-1
Schweitzer Classification
Other editions
Additional editions
Ulrich Golze
VLSI Chip Design with the Hardware Description Language VERILOG
An Introduction Based on a Large RISC Processor Design
Book
01/1996
Springer
€85.59
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Persons
Prof. Dr. Ulrich Golze ist Professor für den Entwurf integrierter Schaltungen an der TU Braunschweig.
Content
Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.- External Specification of Behavior.- Internal Specification of Coarse Structure.- Internal Specification of Coarse Structure.- Pipeline of the Coarse Structure Model.- Pipeline of the Coarse Structure Model.- Synthesis of Gate Model.- Synthesis of Gate Model.- Testing, Testability, Tester, and Testboard.- Testing, Testability, Tester, and Testboard.- Summary and Prospect.- Summary and Prospect.- HDL Models for Circuits and Architectures.- HDL Modeling with VERILOG.