VLSI Chip Design with the Hardware Description Language VERILOG
An Introduction Based on a Large RISC Processor Design
Published on 15. January 1996
Book
Hardback
XIV, 360 pages
978-3-540-60032-9 (ISBN)
Description
The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
More details
Language
English
Place of publication
Heidelberg
Germany
Publishing group
Springer Berlin
Target group
College/higher education
Professional and scholarly
Illustrations
37
80 s/w Tabellen, 37 s/w Abbildungen
37 black & white illustrations, 80 black & white tables, biography
Dimensions
Height: 23.5 cm
Width: 15.5 cm
Weight
720 gr
ISBN-13
978-3-540-60032-9 (9783540600329)
DOI
10.1007/978-3-642-61001-1
Schweitzer Classification
Other editions
Additional editions
Ulrich Golze
VLSI Chip Design with the Hardware Description Language VERILOG
An Introduction Based on a Large RISC Processor Design
Book
08/2014
Springer
€53.49
Shipment within 7-9 days
Persons
Content
Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.- External Specification of Behavior.- Internal Specification of Coarse Structure.- Internal Specification of Coarse Structure.- Pipeline of the Coarse Structure Model.- Pipeline of the Coarse Structure Model.- Synthesis of Gate Model.- Synthesis of Gate Model.- Testing, Testability, Tester, and Testboard.- Testing, Testability, Tester, and Testboard.- Summary and Prospect.- Summary and Prospect.- HDL Models for Circuits and Architectures.- HDL Modeling with VERILOG.