Architecture-Independent Loop Parallelisation
Published on 14. June 2000
Book
Hardback
XVIII, 172 pages
978-1-85233-284-6 (ISBN)
Description
Architecture-independent programming and automatic parallelisation have long been regarded as two different means of alleviating the prohibitive costs of parallel software development. Building on recent advances in both areas, Architecture-Independent Loop Parallelisation proposes a unified approach to the parallelisation of scientific computing code. This novel approach is based on the bulk-synchronous parallel model of computation, and succeeds in automatically generating parallel code that is architecture-independent, scalable, and of analytically predictable performance.
More details
Series
Edition
1st Edition.
Language
English
Place of publication
London
United Kingdom
Target group
College/higher education
Professional and scholarly
Research
Illustrations
biography
Dimensions
Height: 241 mm
Weight
440 gr
ISBN-13
978-1-85233-284-6 (9781852332846)
DOI
10.1007/978-1-4471-0763-7
Schweitzer Classification
Other editions
Additional editions
Radu C. Calinescu
Architecture-Independent Loop Parallelisation
E-Book
12/2012
Springer
€96.29
Available for download
Radu C. Calinescu
Architecture-Independent Loop Parallelisation
Book
09/2011
Springer
€106.99
Shipment within 15-20 days
Content
INTRODUCTION: Motivation. Parallelisation approach proposed in the book. Organisation of the book.- THE BULK-SYNCHRONOUS PARALLEL MODEL: Introduction. Bulk-synchronous parallel computers. The BSP programming model. The BSP cost model. Assessing the efficiency of BSP code. The development of BSP applications. BSP pseudocode.- DATA DEPENDENCE ANALYSIS AND CODE TRANSFORMATION: Introduction. Data dependence. Code transformation techniques.- COMMUNICATION OVERHEADS IN LOOP NEST SCHEDULING: Introduction. Related work. Communication overheads due to input data. Inter-tile communication overheads. Summary.- TEMPLATE-MATCHING PARALLELISATION: Introduction. Related work. Communication-free scheduling. Wavefront block scheduling. Iterative scheduling. Reduction scheduling. Recurrence scheduling. Scheduling broadcast loop nests. Summary.- GENERIC LOOP NEST PARALLELISATION: Introduction. Related work. Data dependence analysis. Potential parallelism identification. Data and computation partitioning. Communication and synchronisation generation. Performance analysis. Summary.- A STRATEGY AND A TOOL FOR ARCHITECTURE-INDEPENDENT LOOP PARALLELISATION: Introduction. Related work. A two-phase strategy for loop nest parallelisation. BSPscheduler: an architecture-independent loop paralleliser. Summary.- THE EFFECTIVENESS OF ARCHITECTURE-INDEPENDENT LOOP PARALLELISATION: Introduction. Matrix-vector and matrix-matrix multiplication. LU decomposition. Algebraic path problem. Finite difference iteration on a Cartesian grid. Merging. Summary.- CONCLUSIONS: Summary of contributions and concluding remarks. Future work directions.- A: THEOREM PROOFS.- B: SYNTAX OF THE BSPSCHEDULER INPUT LANGUAGE.- C: SYNTAX OF THE BSPSCHEDULER OUTPUT LANGUAGE.- D: AUTOMATICALLY GENERATED CODE FOR EXAMPLE 7.5.- Bibliography.- Index.