Phase-Lock Basics 2e
Published on 14. March 2007
Software
Other digital
472 pages
978-0-470-17873-7 (ISBN)
Description
Broad-based and hands-on, Phase-Lock Basics, Second Edition is both easy to understand and easy to customize. The text can be used as a theoretical introduction for graduate students or, when used with MATLAB simulation software, the book becomes a virtual laboratory for working professionals who want to improve their understanding of the design process and apply it to the demands of specific situations. This second edition features a large body of new statistical data obtained from simulations and uses available experimental data for confirmation of the simulation results.
More details
Language
English
Place of publication
Hoboken
United Kingdom
Publishing group
John Wiley and Sons Ltd
Target group
Professional and scholarly
ISBN-13
978-0-470-17873-7 (9780470178737)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
William F. Egan
Phase-Lock Basics
E-Book
06/2008
2nd Edition
Wiley-IEEE Press
€141.99
Available for download
Person
William F. Egan, PhD, is Lecturer in Electrical Engineering at Santa Clara University, California, and formerly a principal engineer at TRW ESD and a senior technologist at GTE Government Systems. He received his PhD in electrical engineering from Stanford University.
Content
Preface. Symbols List and Glossary. Getting Files from The Wiley Ftp Internet Site. PART 1. PHASE LOCK WITHOUT NOISE. 1. INTRODUCTION. 1.1 What is a phase-locked loop (PLL)?. 1.2 Why use a phase-locked loop?. 1.3 Scope of This Book. 1.4 Basic Loop. 1.5 Phase Definitions. 1.6 Phase Detector. 1.7 Combined Gain. 1.8 Operating Range. 1.9 Units and the Laplace Variable s. 2. THE BASIC LOOP. 2.1 Steady-State Conditions. 2.2 Classical Analysis. 2.3 Mathematical Block Diagram. 2.4 Bode Plot. 2.5 Note on Phase Reversals. 2.6 Summary of Transient Responses of the First Order Loop. 3. LOOP COMPONENTS. 3.1 Phase Detector. 3.2 Voltage Controlled Oscillator (VCO). 3.3 Loop Filter. 3.3.3.2 Unintended Poles. 3.4 Filter Reference Voltage. 3.5 Note On the Form of the Filter Equation. 3.6 Capacitors in Loop Filters. 3.7 Higher-Order Filters. 4. LOOP RESPONSE . 4.1 Loop Order and Type. 4.2 Closed-Loop Equations. 4.3 Open-Loop Equations--Lag-Lead Filter. 4.4 Loop with a Lag Filter. 4.5 Loop With an Integrator-and-Lead Filter. 4.6 Summary of Equations. 5. LOOP STABILITY. 5.1 Observing the Open-Loop Response. 5.2 Methods of Stability Analysis and Measures of Stability. 5.3 Stability of Various PLL Configurations. 5.4 Computing Open-Loop Gain and Phase. 5.5 Phase Margin versus Damping Factor. 6. TRANSIENT RESPONSE. 6.1 Step Response. 6.2 Envelope of the Long-Term Step Response. 6.3 Response to Ramp Input. 6.4 Response to Parabolic Input. 6.5 Other Responses. 6.6 Note on Units for Graphs. 6.7 Equivalent Circuit. 6.8 General Long-Term (Steady-State) Response Characteristics. 6.9 Open-Loop Equations in Terms of Closed-Loop Parameters. 6.10 More Complex Loops and State Space Analysis. 6.11 An Approximate Solution Using State-Space Variables. 6.12 Effect of an Added Pole. 7. MODULATION RESPONSE. 7.1 Phase and Frequency Modulation. 7.2 Modulation Responses. 7.3 Responses in a First-Order Loop. 7.4 Transfer Functions in a Second-Order Loop. 7.5 Transient Responses Between Various Points. 7.6 Magnitude and Phase of the Transfer Functions. 7.7 Related Responses. 7.8 Modulation and Demodulation in the Second-Order Loop. 7.9 Measurement of Loop Parameters for α = 0 or 1 from Modulation Responses. 7.10 Effect of an Added Pole. 8. ACQUISITION. 8.1 Overview. 8.2 Acquisition and Lock In a First-Order Loop. 8.3 Acquisition Formulas For Second-Order Loops With Sine Phase Detectors. 8.4 Approximate Pull-In Analysis. 8.5 Phase Plane Analysis. 8.6 Pull Out. 8.7 Effect of Offsets. 8.8 Effect of Component Saturation. 8.9 Hang-up. 8.10 Simulation of the Nonlinear loop. 9. ACQUISITION AIDS. 9.1 Coherent Detection - Lock Indicator. 9.2 Changing Loop Parameters Temporarily. 9.3 Automatic Tuning of ω<sub>c</sub> --Frequency Discriminator. 9.4 Acquisition Aiding Logic. 9.5 Sweeping ω<sub>c</sub>, Type-2 Loop. 9.6 Sweep Circuits. 10. APPLICATIONS AND EXTENSIONS. 10.1 Higher Order Loops. 10.2 Generalized Voltage-Controlled Oscillator. 10.3 Long Loop. 10.4 Carrier Recovery. 10.5 Data Synchronization. 10.6 Clock and Data Timing Control. 10.7 All-Digital Phase-Locked Loop (ADPLL). 10.8 Summary. PART 2. PHASE LOCK IN NOISE. 11. PHASE MODULATION BY NOISE. 11.1 Representation of Noise Modulation. 11.2 Processing of Noise Modulation by the Phase-Locked Loop. 11.3 Phase and Frequency Variance. 11.4 Typical Oscillator Spectrums. 11.5 Limits on the Noise Spectrum -- Infinite Variances. 11.6 Power Spectrum. 11.7 Frequency Multiplication and Division. 11.8 Other Representations. 12. RESPONSE TO PHASE NOISE. 12.1 Processing of Reference Phase Noise. 12.2 Processing of VCO Phase Noise. 12.3 Harmful Effect of Phase Noise in Radio Receivers. 12.4 Superposition. 12.5 Optimum Loop with Both Input and VCO Noise. 12.6 Multiple Loops. 12.7 Effects of Noise Injected Elsewhere. 12.8 Measuring Phase Noise. 13. REPRESENTATION OF ADDITIVE NOISE. 13.1 General. 13.2 Phase Modulation On the Signal. 13.3 Multiplicative Modulation On Quadrature Carriers. 13.4 Noise at the Phase Detector Output. 13.5 Restrictions on the Noise Models. 13.6 Does The Loop Lock to the Additive Noise?. 13.7 Other Types of Phase Detectors in the Presence of Noise. 13.8 Modified PD Characteristic With Noise. 14. LOOP RESPONSE TO ADDITIVE NOISE. 14.1 Noise Bandwidth. 14.2 Signal-to-Noise in the Loop Bandwidth. 14.3 Loop Optimization in the Presence of Noise. 14.3.4 Optimum Loop for a Frequency Step Input. 14.3.5 Optimum Loop for a Frequency Ramp Input. 15. PHASE-LOCKED LOOP AS A DEMODULATOR. 15.1 Phase Demodulation. 15.2 Frequency Demodulation, Bandwidth Set By a Filter. 15.3 Frequency Discriminator, First-Order Loop. 15.4 Frequency Discriminator, Second-Order Loop. 15.5 Expected Phase Error. 15.6 Summary of Frequency Discriminator S/N. 15.7 Standard Discriminator and Click Noise. 15.8 Clicks with a PLL. 15.9 Noise in a Carrier Recovery Loop. 16. PARAMETER VARIATION DUE TO NOISE. 16.1 Preview. 16.2 AGC. 16.3 Limiter. 16.4 Effects of Gain Variation on Loop Parameters. 16.5 Effect of AGC or Limiter on an Optimized Loop. 17. CYCLE SKIPPING DUE TO NOISE. 17.1 Output Phase. 17.2 Cycle Skipping, Mean Time. 17.3 Cycle Skipping, Mean Frequency. 17.4 Cycle Skipping with Mistuning. 17.5 Summary. 18. NON-LINEAR OPERATION IN A LOCKED LOOP. 18.1 Notation. 18.2 Phase-Detector Output u1. 18.3 Changes in the Output Spectrum. 18.4 Gain Suppression, Quasi-Linear Approximation. 19. ACQUISITION AIDS IN THE PRESENCE OF NOISE. 19.1 Sweeping with Plain Closed-Loop. 19.2 Reduction of Coherent Detector Output (Closed-Loop Sweeping). 19.3 Closed-Loop Sweeping in Noise with Coherent Detector. 20. BAND-LIMITED NOISE. 20.1 Signals Centered in a Noise Band. 20.2 Eccentric Signals. 20.3 Extension to Other Types of Interference. 21. FURTHER INFORMATION . 21.1 Sources for Additional Studies in Phase Lock. 21.2 Sources Covering Phase-Locked Frequency Synthesis.