Multirate Switched-Capacitor Circuits for 2-D Signal Processing
Published on 6. December 2012
XXI, 124 pages
978-1-4615-5523-0 (ISBN)
Description
Multirate Switched-Capacitor Circuits for 2-D Signal Processing introduces the concepts of analog multirate signal processing for the efficient implementation of two-dimensional (2-D) filtering in integrated circuit form, particularly from the viewpoints of silicon area and power dissipation. New 2-D switched-capacitor (SC) networks and design techniques are presented, both with finite impulse response (FIR) and infinite impulse response (IIR) with separable denominator polynomial, which offer simpler and more systematic synthesis procedures than currently available design techniques for 2-D analog filters. Since they are in the discrete-time domain, the book can be also referred to the digital multirate signal processing.
A 2-D SC image processor that realizes both (2 x 2)nd-order Butterworth lowpass and highpass filtering functions for video image signals was realized as a prototype integrated circuit implemented in 1.0-mum CMOS technology. The experimental characterization of this prototype chip demonstrated the feasibility of real-time analog multirate 2-D image processing with equivalent 8-bits accuracy, using only 2.5 x 3.0 mm2 of silicon area and dissipating as little as 85 mW at 5V supply and 18 MHz sampling rate. This indicates that for moderate accuracy and low to moderate complexity of the filtering function, a fully multirate analog implementation has a potential to achieve a more competitive implementation than an alternative digital VLSI implementation. However, for high accuracy and/or higher processing complexity, not only the relative overhead cost of the front-end and back-end converters will diminish but also the implementation of the processing core in digital VLSI will benefit more of technology scaling to achieve higher density of integration.
Multirate Switched-Capacitor Circuits for 2-D Signal Processing is essential reading for practicing analog design engineers and researchers in the field. It is also suitable as a text for an advanced course on the subject.
A 2-D SC image processor that realizes both (2 x 2)nd-order Butterworth lowpass and highpass filtering functions for video image signals was realized as a prototype integrated circuit implemented in 1.0-mum CMOS technology. The experimental characterization of this prototype chip demonstrated the feasibility of real-time analog multirate 2-D image processing with equivalent 8-bits accuracy, using only 2.5 x 3.0 mm2 of silicon area and dissipating as little as 85 mW at 5V supply and 18 MHz sampling rate. This indicates that for moderate accuracy and low to moderate complexity of the filtering function, a fully multirate analog implementation has a potential to achieve a more competitive implementation than an alternative digital VLSI implementation. However, for high accuracy and/or higher processing complexity, not only the relative overhead cost of the front-end and back-end converters will diminish but also the implementation of the processing core in digital VLSI will benefit more of technology scaling to achieve higher density of integration.
Multirate Switched-Capacitor Circuits for 2-D Signal Processing is essential reading for practicing analog design engineers and researchers in the field. It is also suitable as a text for an advanced course on the subject.
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Other editions
Additional editions
Wang Ping | José E. Franca
Multirate Switched-Capacitor Circuits for 2-D Signal Processing
Book
11/2012
Springer
€160.49
Shipment within 7-9 days
Wang Ping | José E. Franca
Multirate Switched-Capacitor Circuits for 2-D Signal Processing
Book
11/1997
Kluwer Academic Publishers
€164.50
Shipment within 15-20 days
Content
1 Introduction.- 1.1 Introductory Remarks.- 1.2 Book Outline.- References.- 2 2-D Signals and Filtering Systems.- 2.1 Introduction.- 2.2 2-D Signals.- 2.3 2-D Image Filtering Systems.- 2.4 Hardware Implementation of 2-D Filters.- 2.5 Application Examples of 2-D Filter Systems.- 2.6 Summary.- References.- 3 Fundamental Aspects of 2-D Decimation Filters.- 3.1 Introduction.- 3.2 1-D Decimation.- 3.3 2-D Decimation.- 3.4 Delay-Line Memory Requirements for 2-D Filters.- 3.5 Summary.- References.- 4 Polyphase-Coefficient Structures for 2-D Decimation Filters.- 4.1 Introduction.- 4.2 Modified 1-D Decimation Polyphase Structures.- 4.3 Polyphase-Coefficient Structures for 2-D Decimation Filters.- 4.4 Summary.- References.- 5 SC Architectures for 2-D Decimation Filters in Polyphase-Coefficient Form.- 5.1 Introduction.- 5.2 SC Building Blocks.- 5.3 SC Architectures with 2-D Polyphase-Coefficients.- 5.4 Design Example of an FIR 2-D Decimation Filter.- 5.5 Design Example of an IIR 2-D Decimation Filter.- 5.6 Summary.- References.- 6 A Real-Time 2-D Analog Multirate Image Processor in 1.0-µm CMOS Technology.- 6.1 Introduction.- 6.2 2-D Multirate Filter Design.- 6.3 SC Horizontal Decimation Filter.- 6.4 SC Vertical Filter and Associated Delay-Line Memory Blocks.- 6.5 Integrated Circuit Implementation.- 6.6 Experimental Characterization.- 6.7 Summary.- References.
