High-Performance Computing Using FPGAs
1st Edition
Published on 23. August 2013
XI, 803 pages
978-1-4614-1791-0 (ISBN)
Description
High-Performance Computing using FPGA covers the area of high performance reconfigurable computing (HPRC). This book provides an overview of architectures, tools and applications for High-Performance Reconfigurable Computing (HPRC). FPGAs offer very high I/O bandwidth and fine-grained, custom and flexible parallelism and with the ever-increasing computational needs coupled with the frequency/power wall, the increasing maturity and capabilities of FPGAs, and the advent of multicore processors which has caused the acceptance of parallel computational models. The Part on architectures will introduce different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHREC's Novo-G and EPCC's Maxwell systems; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFL's CONFETTI system. The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on C-to-Gate tools (such as Impulse-C, AutoESL, Handel-C, MORA-C++); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsoft's Kiwi and Alchemy projects). The part on Applications will present case from several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling.
More details
Series
Language
English
Place of publication
New York
United States
Publishing group
Springer US
Target group
Professional and scholarly
Product notice
Reflowable
Illustrations
XI, 803 p. 232 illus.
File size
32,09 MB
ISBN-13
978-1-4614-1791-0 (9781461417910)
DOI
10.1007/978-1-4614-1791-0
Schweitzer Classification
Other editions
Additional editions
Wim Vanderbauwhede | Khaled Benkrid
High-Performance Computing Using FPGAs
Book
05/2013
Springer
€267.49
Shipment within 15-20 days
Persons
Wim Vanderbauwhede is currently a Lecturer at the Department of Computing Science of the University of Glasgow.
Dr. Benkrid is currently a Senior Lecturer at School of Engineering and Electronics at The University of Edinburgh.
Dr. Benkrid is currently a Senior Lecturer at School of Engineering and Electronics at The University of Edinburgh.
Content
High-Performance Hardware Acceleration of Asset Simulations.- Monte Carlo Simulation based Financial Computing on the Maxwell FPGA Parallel Machine.- Bioinformatics Applications on the FPGA-based High-Performance Computer RIVYERA.- FPGA-Accelerated Molecular Dynamics.- FPGA-based HPRC for Bioinformatics Applications.- High-Performance Computing for Neuroinformatics using FPGA.- High-Performance FPGA-Accelerated Real-time Search.- High-Performance Data Processing over N-ary Trees.- FPGA-based Systolic Computational-Memory Array for Scalable Stencil Computations.- High performance implementation of RTM seismic modeling on FPGAs: architecture, arithmetic and power issues.- High-Performance Cryptanalysis on RIVYERA and COPACOBANA Computing Systems.- FPGA-based HPRC Systems for Scientific Applications.- Accelerating the SPICE Circuit Simulator using an FPGA - A Case Study.- The Convey Hybrid-Core Architecture.- Low Cost High Performance Reconfigurable Computing.- An FPGA-based supercomputer for statistical physics: the weird case of Janus.- Accelerate Communication, not Computation!.- High-speed torus interconnect using FPGAs.- MEMSCALE: Re-architecting memory resources for clusters.- High-performance computing based on high-speed dynamic reconfiguration.- Reconfigurable arithmetic for HPC.- Acceleration of the Discrete Element Method: From RTL to C-Based Design.- Optimising Euroben Kernels on Maxwell.- Assessing Productivity of High-Level Design Methodologies for High-Performance Reconfigurable Computers.- Maximum performance computing with dataflow engines.
