Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

Name: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation | 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers
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20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers

Rene Van Leuken Gilles Sicard(Editor)

Springer (Publisher)

Published on 16. January 2011

XII, 260 pages

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978-3-642-17752-1 (ISBN)

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Content

Title Page
Preface
Organization
Table of Contents
Session 1: Design Flows
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC
Introduction
Related Work
Power-Aware Streaming Application Scheduling
Implementation
Results
Conclusion
References
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software
Introduction
Related Work
Automated Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software
Run-Time Power Profiling Based on Power Emulation
Power-Critical Code Region Detection
Optimization of Power-Critical Source Code Regions
Experimental Results
Test System for Power Peak Optimization
Comparison of Original and Optimized Power Consumption and Supply Voltage Profiles
Impact of Power Peak Optimization on Execution Time and Code Size
Conclusions
References
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk
Introduction
Related Work
Modeling of Dynamic Power Dissipation on Links
Bit Level Statistics
Simulation Results
Simulation Accuracy
Simulation Performance
Conclusion
References
Residue Arithmetic for Designing Low-Power Multiply-Add Units
Introduction
Review of RNS Basics
Low-Power in RNS
RNS and Binary Multiply-Add Units
Results and Comparisons
Conclusions
References
Session 2: Circuit Techniques 1
An On-Chip Flip-Flop Characterization Circuit
Introduction
Binary and Quaternary Look-Up Tables Overview
Look-Up Tables Implementation
Quaternary-to-Binary Converter
Binary vs Quaternary Look-Up Tables
Variability and Noise Margin in Quaternary Circuits
Conclusions
References
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion
Introduction
MOSFET Biased in Weak Inversion as a Trans-linear Element
MOSFET in Weak Inversion
Trans-linear Principle
Companding Method and Log-Domain Filters
Circuit Design and Simulation Results
Circuit Design
CADENCE Simulation Results
Discussion and Conclusions
References
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits
Introduction
Framework for FFs Comparison and Selected FF Topologies
Adopted Analysis/ Design Strategies and Inclusion of Layout Impact
High-Speed FF Topologies: Pulsed and Differential Classes
Energy-Delay Tradeoff and Energy-Efficient Curves
Pulsed FFs
Differential FFs
Area and Tradeoff with Delay
Conclusion
References
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework
Introduction
Related Work
Time-Dependent Dielectric Breakdown Mechanism
The Proposed Interconnect Reliability Framework
Estimation of Delay Impact on Interconnects
Evaluation of the TDDB Framework to a LEON3-Based MP-SoC
Experimental Results and Discussion
Conclusion and Hints for Future Work
References
Session 3: Low Power Circuits
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
Introduction
Binary and Quaternary Look-Up Tables Overview
Look-Up Tables Implementation
Quaternary-to-Binary Converter
Binary vs Quaternary Look-Up Tables
Variability and Noise Margin in Quaternary Circuits
Conclusions
References
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS
Introduction
Low Power GALS NoC Architecture
IP Unit Integration for Power Optimization
Local DVFS Using Two Voltages Set Points
Local DVFS Control
NI Task Synchronization
Core Task Synchronization
Local On-Line Optimization
Case Study on a 3GPP LTE Telecom Application
Simulation Platform and Applicative Scenarios
Obtained Energy Savings
Conclusions
References
Self-Timed SRAM for Energy Harvesting Systems
Introduction
Existing Asynchronous SRAM Memory
Latency Investigation on SRAM Cells under Different Vdds
Asynchronous SRAM Solutions
Intuitive Speed Independent SRAM
More Practical Speed Independent SRAM
A Possible Bundled SRAM Based on SI Delay Elements
1Kb Memory Bank Design and Measurements
Conclusions and Future Work
References
L1 Data Cache Power Reduction Using a Forwarding Predictor
Introduction
Background
Filtering DL1 Accesses Using a Forwarding Predictor
Rationale
Overall Structure
Supporting Coherence and Consistency
Experimental Framework
Evaluation
Main Results
Forwarding Predictors
Conclusions
References
Session 4: Self-Timed Circuits
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations
Introduction
Background
Dual-Vth Circuit Design
Timed Petri-NET
Statistical Dual Vth Asynchronous Circuits Design Framework
A Vth-Assignment Algorithm
Statistical Mathematical Operations
Performance and Leakage Power Analysis
Fitness Function
Experimental Results
Conclusions
References
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case
Introduction
Self-Timed Rings
Propagation Rules
Configurability
Phase Noise
C-Element Implementations
Design of the Ring Stages
Designing with the Logical Effort Method
Designing with Electrical Simulations
Modified Self-Timed Ring Stage
Performances Comparison
Conclusions
References
Hermes-A - An Asynchronous NoC Router with Distributed Routing
Introduction
Related Work
The Hermes-A Router Architecture
Network Interface
ASIC Implementation
Conclusions and Future Work
References
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip
Introduction
Probability-Multiplex Coding
Dynamic Power Considerations
Static Power Considerations
Analysis of Probability-Coding in NoCs with VC
Experimental Results
Conclusions
References
Session 5: Process Variation
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing
Introduction
Intra-die Random Variability
Conventional PV Compensation Techniques
Performance Degradation Due to Random PV versus VDD
Proposed Idea
Simulation Results
Discussions
Details of the LP-S and HP-F Circuits
References
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis
Introduction
Pulsed Flip-Flop Topologies and Simulation Methodology
Circuit-Level Techniques to Improve Yield
Comparative Analysis and Discussion
Conclusions
References
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
Introduction
GLM Limitations and Optimization Trends
Statistical Simplified Transistor Model (SSTM)
Current Source Modeling
Intrinsic Capacitance Modeling
Non-MC Statistical Simulator
Experimental Results
Conclusion
References
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation
Introduction
Current Source Modeling
White-Box CSM Characterization
Nominal Characterization
Handling Parameter Variations
Implementation
Results
Conclusion
References
Session 6: Circuit Techniques 2
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer
Introduction
Functioning Principle of the Solution
Theoritical Aspect of the Solution
Precision
Switching Time
Frequency Bandwidth
Implementation Results
Conclusion
References
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis
Introduction
Digitally Controlled Oscillator
Clock Divider
Phase Frequency Detector
Control Unit
Linear - Non-linear Controller
Recursive Filter
Smoothing Recursive Filter
Chip Layout
Simulation and Experimental Results
Conclusion
References
Clock Network Synthesis with Concurrent Gate Insertion
Introduction
Preliminaries
Clock Tree and Controller Tree
Switched Capacitance
Methodology
Power Aware Topology Generation
Concurrent Gate and Buffer Insertion
Experimental Results
Conclusion
References
Modeling Time Domain Magnetic Emissions of ICs
Introduction
Magnetic Field Simulation Flow
Basic Concept
Current Extraction Step
Magnetic Field Calculation Step
Additional Mandatory Steps
Validation
Conclusion
References
Special Session 1: High-Level Modeling of Power-Aware Heterogeneous Designs in SystemC-AMS (Abstracts)
Power Profiling of Embedded Analog/Mixed-Signal Systems
Open-People: Open Power and Energy Optimization PLatform and Estimator
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems
OPENTLM and SOCKET: Creating an OpenEco System for Virtual Prototyping of Complex SOCs
Keynotes (Abstracts)
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges
Signing Off Industrial Designs on Evolving Technologies
Author Index

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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