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Growth of Nano-Wire Field Effect Transistor in 21st Century

Kunal Sinha

Dept. of Electronics, Asutosh College, Kolkata, India

Abstract

The Nanowire Field-Effect-Transistor (NW-FET) is one of the leading transistor architectures which are under the observation of the research community for the future technology node, predicted by the International Technology Roadmap for Semiconductors (ITRS). With the gradual reduction of transistor dimensions following Moore's law, the existing transistors like FinFET, Tri-Gate MOSFET, etc. are already under pressure to maintain the short channel effects (SCEs) of the transistor within control, and also provide improved performance. With 7/10 nm technology node transistors already under production in several applications, researchers are exploring nanowire structures for future technology node architectures. The initial results from theoretical and simulation studies motivated the researchers to fabricate the NW-FET device, and the fabricated device is also showing impressive output thus researchers are also exploring the feasibility of this device for other possible cutting-edge applications. In this chapter, various theoretical, simulation results from published reports are going to be discussed. Later on, the output results from the fabricated NW-FET device and how this structure can be utilized in future applications will be briefed with appropriate references. In short, this chapter will brief how the research work on NW-FET devices has grown in the 21st century.

Keywords: Nanowire (NW), field effect transistor (FET), MOSFET, FinFET, NW-FET, sensor

1.1 Introduction

The rapid development in the field of Nanoscience and Nanotechnology in the last few decades led the research community to evolve the transistor device from conventional Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) structures to various 3-dimensional (3D) devices like Fin-FET, Gate-All-Around FET (GAA), and Nano-wire FET (NW-FET). The reason for such evolution of transistor structure is due to the rapid demand for a smaller dimensional transistor with improved performance. The rate of reduction of transistor size is achieved by following the famous Moore's Law, where Gordon Moore predicted that "The number of Transistors in an Integrated Circuit (IC) will double every 18 months" [1]. In the last few decades, by continuous downscaling of transistor dimensions and supply voltage, the continuous demand for higher packing density with low cost per function has been achieved. The increase of packing density in an IC also results in higher circuit speed and lower power dissipation. This inspires the researchers to sustain the growth of the semiconductor industry by reducing the transistor dimension and accordingly the supply voltage. However, as the dimensions start approaching the nano-scale domain (<100 nm), various new observations are recorded by several researchers in the device performance due to low dimensional device structures. This collection of undesirable device problems is termed "short channel effects" which include a reduction of threshold voltage with the decrease of channel length, increase of Drain-Induced-Barrier-Lowering (DIBL) effect, degradation of sub-threshold slope, resulting in higher off-state current, high gate-to-substrate tunneling current through the thin gate oxide region and so on. These short channel effects made the researcher think before reducing the conventional MOSFET dimensions further and developing some new transistor structures to overcome the above challenges [2-5]. On the other hand, basic semiconductor material properties like carrier mobility, channel conductivity, etc. cannot be scaled with the reduction of MOSFET channel length beyond 100 nm, and as a result, researchers started to explore improving the channel properties in such dimensional devices. In this regard, the application of strain technology, and various other channel materials are reported by various scientists and these are very well explored and documented in [6-12].

Following the guidelines of the International Technology Roadmap for Semiconductors (ITRS), the scaling of conventional MOSFET continued till the 65 nm technology node and after that, the semiconductor industry started using the advanced MOSFET structure like dual-gate MOSFET, FinFET, Gate-All-Around (GAA) FET, etc. These devices offer less prone to the short channel effects and help to sustain the technological advancement even in sub-10 nm technology node device structures. Among these devices, the FinFET device structure becomes the most popular and various semiconductor companies like Samsung, Global Foundries, TSMC, IMEC, etc. are using this structure for various applications like processors, amplifiers, etc. Although the FinFET is the leading architecture for modern high-performance applications, however, it has its limitations for technology nodes 10 nm or less.

As an alternative to FinFET devices, researchers are exploring Nanosheet (NS) and Nano-wire (NW) based FET devices [13-16] and reported the findings in reputed journals and conferences. The performance comparison between FinFET and these NS-FET and NW-FET devices are also reported by researchers in several reputed literatures [17-22] and indicates that these modern devices have enough potential to sustain the growth of technology for future days. In this chapter, the growth of NW-FET devices in the 21st century is going to be discussed. Several researchers have reported their findings on this device structure in reputed journals and conferences and these reports are summarized for a clear understanding of this architecture and how it can be utilized in the coming years. In section 1.2, the initial studies on this device structure will be discussed. Then in section III, various observations are going to be discussed that are obtained from fabricated NW device structures by researchers in leading laboratories. The application of NW-FET for different modern applications is reported in the latest journals and briefed in section 1.4. Finally, in the last section, a conclusion will be drawn with a summary of various publications in the 21st century.

1.2 Initial Works on Nanowire Field-Effect-Transistors (NW-FET)

The Nanowire Field-Effect-Transistor is accepted not only by the academic community but by the semiconductor industry as well since its inception. The physics of the operation of the device is extremely critical and extensively studied through various in-depth simulations by various scientists with the help of modern quantum simulators, along with that detailed theoretical analyses performed by several researchers to validate the simulation studies. The concept of NW-FET starts developing from the inception of carbon nanotube, reported by Iijima [23], and various researchers started exploring different 1 dimensional (1D) nano-scale structures and this research of 1D structures led to the discovery of nano-wire (NW) and nano-rod (NR) architectures. After careful analysis of the different dimensions of various NW and NR architectures, it has been concluded that an NW will have a length and width ratio of 10:1 [24]. Furthermore, the transport of carriers through an NW will be strictly one-dimensional (1D) in nature. The 1D transport property of NW attracts the researchers to use it in the transistor channel region, to eliminate the current loss due to lateral carrier scattering, and high mobility between source and drain regions offers higher drive current compared to other contemporary transistor architectures. Apart from the use of NW as transistor channel material, in the present scenario, these NWs are used in various interconnect and several other nano-electronic and optoelectronic devices also. In the following sections, the results of NW-FET performance studies, published in various journals, are going to be discussed.

1.2(A) Theoretical and Simulation Studies on Nanowire FET (NW-FET)

The impact of crystal orientation and band structure in silicon (Si) and germanium (Ge) NW-FET devices are studied in detail by Wang et al. [25] with the help of the sp3d5s* tight binding approach. The simulation study of ballistic Si and Ge NW-FET includes the variation of channel diameter as well. From their investigation, it is found that <110> is the optimum orientation for obtaining the best result from both Si and Ge NW-FET, having a diameter of 3 nm. Furthermore, the pFET performance speed is found to be increasing monotonically with decreasing the NW diameter; however, in the case of nFET, the performance speed depends more on the orientation and material type of the NW. The researchers in other laboratories observed that for carbon nanotube structures, the carrier transport is ballistic in nature [26], but for Si or Ge architecture, carriers suffer strong scattering loss in such conditions [27]. In the present scenario, FinFET technology is the leading architecture for modern-day processors and other applications, used by all leading semiconductor manufacturers. However, for advanced CMOS devices, this transistor architecture will not be able to perform e?ciently and scientists are considering NW-FET as a possible alternative to FinFET devices. In this regard, Nagy et al. have compared the performance of FinFET and NW-FET architecture and reported their findings recently in [28]. The studies are performed by using the 3D finite-element drift-diffusion and Monte Carlo simulation to include the quantization...