Advanced Parallel Processing Technologies
9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011, Proceedings
Published on 15. September 2011
190 pages
978-3-642-24151-2 (ISBN)
Description
This book constitutes the refereed proceedings of the 9th International Symposium on Advanced Parallel Processing Technologies, APPT 2011, held in Shanghai, China, in September 2011.
The 13 revised full papers presented were carefully reviewed and selected from 40 submissions.
The papers are organized in topical sections on parallel distributed system architectures, architecture, parallel application and software, distributed and cloud computing.
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Olivier Temam | Pen-Chung Yew | Binyu Zang
Advanced Parallel Processing Technologies
9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011, Proceedings
Book
09/2011
Springer
€53.49
Shipment within 7-9 days
Content
- Title
- Preface
- Organization
- Table of Contents
- Reconstructing Hardware Transactional Memory for Workload Optimized Systems
- Introduction
- Synchronization Bottleneck and TM as a Solution
- Revisiting HTM for Workload Optimized Systems
- Contributions of this Paper
- Relaxation of the Criteria for a HTM
- Exploration of HTM Design Choices
- Base HTM Design Choices
- Enhanced HTM Design Choices
- Experimental Work
- Experimental Setup A
- Experimental Setup B
- Conclusion
- References
- Enhanced Adaptive Insertion Policy for Shared Caches
- Introduction
- Background and Motivation
- Enhanced Adaptive Insertion Policy
- Enhanced DIP for Single Core
- Enhanced DIP for Shared Caches
- Evaluation
- Simulation Setup
- EDIP Performance for Single Core
- EDIP Performance for Shared Caches
- Hardware Overhead
- Related Work
- Conclusions and Future Work
- References
- A Read-Write Aware Replacement Policy for Phase Change Memory
- Introduction
- Background
- Read-Write Aware Replacement Policy
- Overview
- Read-Write Aware Replacement Policy
- Improved Read-Write Aware Replacement Policy
- Evaluation
- Experiment Setup
- Results on the Organization without DRAM Buffer
- Results on the Organization with DRAM Buffer
- Related Work
- Conclusions and Future Work
- References
- Evaluating the Performance and Scalability of MapReduce Applications on X10
- Introduction
- Background
- An Overview of X10
- Hadoop
- Implementation of Two MapReduce Applications Using X10
- Execution Overview
- Data Structures
- Implementing WordCount and DistributedSort
- Optimization
- Using C++ Native Calls to Process I/O
- Improving the Collecting-Finish Framework
- Evaluation
- Experiment Setup
- Overall Performance on a Single Node with Performance Breakdown
- Overall Performance on the Cluster and Comparison to Hadoop
- Further Optimization Opportunities
- Related Work
- Conclusion and Future Work
- References
- Comparing High Level MapReduce Query Languages
- Introduction
- Related Work
- MapReduce
- Hadoop
- High Level Query Languages
- Language Query Examples
- HLQL Comparison
- Conciseness
- Application Kernels
- Comparative Code Size
- Performance Experiment Design
- Language Versions, Hardware and Operating Systems
- Reducer Tasks
- Key Distribution
- Performance Results
- Scaling Input Size
- Scaling Processing Units
- Proportional Scale Out of Input Size and Processing Units
- Controlling Reducers
- Language Discussion
- Conclusion
- References
- A Semi-automatic Scratchpad Memory Management Framework for CMP
- Introduction
- The Target Architecture
- THE SPMMLIB Runtime System
- Motivation
- Inside the SPMMLIB
- SPMMLIB Application Programming Interface
- Optimization Based on Thread-Data Affinity
- A Case Study
- Evaluation
- Simulation Environment
- Results
- Related Work
- Traditional SPM Management
- SPM Management in CMP with LLM Features
- SPM Management in CMP with PGAS Features
- Conclusion and Future Work
- References
- Parallel Binomial Valuation of American Options with Proportional Transaction Costs
- Introduction
- Related Work
- The Sequential Pricing Algorithms
- The Parallel Algorithm
- Experimental Results
- Conclusion
- References
- A Parallel Analysis on Scale Invariant Feature Transform (SIFT) Algorithm
- Introduction
- Computing SIFT
- SIFT Overview
- Time Analysis of SIFT
- Parallel Characteristics Analysis
- Parallel SIFT Implementation
- Scale Level Parallelism
- Block Level Parallelism
- Experimental Results
- Parallel Performance on 4 Threads
- Block Size Analysis
- Scalability Analysis
- Real Image Evaluation
- Related Work
- Image Local Feature-Based Extraction Algorithms
- Accelerating SIFT Algorithm
- Conclusion and Future Work
- References
- Modality Conflict Discovery for SOA Security Policies
- Introduction
- System Model
- Modality Conflict Discovery for SOA Policies
- Prerequisites
- Preparation Phase
- Modality Conflict Detection Algorithm
- Correctness Proof
- Conclusions
- References
- FPGA Implementation of Variable-Precision Floating-Point Arithmetic
- Introduction
- Background
- Range Reduction
- Methods for Elementary Function
- Custom VLIW Architecture
- Implementation of VV-Processor
- Variable-Precision Floating-Point Format
- Hardware Organization
- Variable-Precision Elementary Function Algorithm
- VP Exponential Function Algorithm
- VP Trigonometric Function Algorithm
- Experiments Result
- Resource Utilization
- Evaluation of VV-Processor
- Performance Comparison with Related Work
- Boost Accelerator
- Conclusion
- References
- Optimization of N-Queens Solvers on Graphics Processors
- Introduction
- Related Work
- Design and Implementation of the Naive N-Queens Kernel
- Optimization
- Optimal Usage of Memory
- Reducing Divergence with the IRRC Approach
- Balancing the Load at Thread Level
- Performance Summary
- Discussion
- Conclusion
- References
- ParTool: A Feedback-Directed Parallelizer
- Introduction
- ROSE Compiler Infrastructure
- ParTool: Design
- Data Flow and Dependence Analysis
- Attaching OpenMP Pragma
- Feedback
- Usefulness of the Feedback Mechanism
- CommandLine Options
- Code Characteristics Suitable for ParTool
- Results
- Comparison of Parallelization Performance
- NAS Parallel Benchmarks
- Real Life Examples
- Other Kernels
- Related Work
- Comparison of GAP with ParTool
- Conclusion
- References
- MT-Profiler: A Parallel Dynamic Analysis Framework Based on Two-Stage Sampling
- Introduction
- Related Work
- The Design of MT-Profiler
- System Overview
- Two-Stage Sampling
- The Monitor
- The Scheduler
- Exported APIs
- Performance Evaluation
- Experiment Setup
- Performance Comparison
- Runtime Overhead
- Effects of Sampling Rate
- Conclusion
- References
- Author Index
