Reliability Wearout Mechanisms in Advanced CMOS Technologies
Published on 4. November 2009
864 pages
978-0-470-45525-8 (ISBN)
Description
This invaluable resource tells the complete story of failure mechanisms--from basic concepts to the tools necessary to conduct reliability tests and analyze the results. Both a text and a reference work for this important area of semiconductor technology, it assumes no reliability education or experience. It also offers the first reference book with all relevant physics, equations, and step-by-step procedures for CMOS technology reliability in one place. Practical appendices provide basic experimental procedures that include experiment design, performing stressing in the laboratory, data analysis, reliability projections, and interpreting projections.
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Alvin W. Strong | Ernest Y. Wu | Rolf-Peter Vollertsen
Reliability Wearout Mechanisms in Advanced CMOS chnologies
Software
10/2009
Wiley
€188.35
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Alvin W. Strong | Ernest Y. Wu | Rolf-Peter Vollertsen
Reliability Wearout Mechanisms in Advanced CMOS Technologies
Book
09/2009
Wiley-IEEE Press
€195.50
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Persons
ALVIN W. STRONG, PhD, is retired from IBM in Essex Junction,Vermont. He holds nineteen patents, has authored or coauthored anumber of papers, and is a member of the IEEE and chair of theJEDEC 14.2 standards subcommittee.
ERNEST Y. WU, PhD, is a Senior Technical Staff Member atSemiconductor Research and Development Center (SRDC) in the IBMSystem and Technology Group. He has authored or coauthored morethan 100 technical or conference papers. His research interestsinclude dielectric/device reliability and electronic physics.
ROLF-PETER VOLLERTSEN, PhD, is a Principal forReliability Methodology at Infineon Technologies AG in Munich,Germany, where he is responsible for methods and test structuresfor fast Wafer Level Reliability monitoring and the implementationof fast WLR methods.
JORDI SUNE, PhD, is Professor of Electronics Engineeringat the Universitat Aut¿noma de Barcelona, Spain. He is SeniorMember of the IEEE and has coauthored over 150 publications onoxide reliability and electron devices. His research interests arein gate oxide physics, reliability statistics, and modeling ofnanometer-scale electron devices.
GIUSEPPE LaROSA, PhD, is Project Leader of the FEOLtechnology reliability qualification activities for the developmentof advanced SOI Logic and eDRAM technologies at IBM, where he isresponsible for the implementation and development ofstate-of-the-art NBTI stress and test methodologies.
TIMOTHY D. SULLIVAN, PhD, is Team Leader formetallization reliability at IBM's Essex Junction facility. Theauthor of numerous technical papers and tutorials, he holdsthirteen patents with several more pending.
STEWART E. RAUCH, III, PhD, is currently a SeniorTechnical Staff Member at the IBM SRDC in New York, where hespecializes in hot carrier and NBTI reliability of state-of-the-artCMOS devices. He is the author of numerous technical papers andtutorials and holds five patents.
Content
Preface.
1 INTRODUCTION (Alvin W. Strong).
1.1 Book Philosophy.
1.2 Lifetime and Acceleration Concepts.
1.3 Mechanism Types.
1.4 Reliability Statistics.
1.5 Chi-Square and Student t Distributions.
1.6 Application.
2 DIELECTRIC CHARACTERIZATION AND RELIABILITYMETHODOLOGY (Ernest Y. Wu, Rolf-Peter Vollertsen, and JordiSune).
2.1 Introduction.
2.2 Fundamentals of Insulator Physics and Characterization.
2.3 Measurement of Dielectric Reliability.
2.4 Fundamentals of Dielectric Breakdown Statistics.
2.5 Summary and Future Trends.
3 DIELECTRIC BREAKDOWN OF GATE OXIDES: PHYSICS ANDEXPERIMENTS (Ernest Y. Wu, Rolf-Peter Vollertsen, and JordiSune).
3.1 Introduction.
3.2 Physics of Degradation and Breakdown.
3.3 Physical Models for Oxide Degradation and Breakdown.
3.4 Experimental Results of Oxide Breakdown.
3.5 Post-Breakdown Phenomena.
4 NEGATIVE BIAS TEMPERATURE INSTABILITIES IN pMOSFETDEVICES (Giuseppe LaRosa).
4.1 Introduction.
4.2 Considerations on NBTI Stress Configurations.
4.3 Appropriate NBTI Stress Bias Dependence.
4.4 Nature of the NBTI Damage.
4.5 Impact of the NBTI Damage to Key pMOSFET TransistorParameters.
4.6 Physical Mechanisms Contributing to the NBTI Damage.
4.7 Key Experimental Observations on the NBTI Damage.
4.8 Nit Generation by Reaction-Diffusion (R-D)Processes.
4.9 Hole Trapping Modeling.
4.10 NBTI Dependence on CMOS Processes.
4.11 NBTI Dependence on Area Scaling.
4.12 Overview of Key NBTI Features.
5 HOT CARRIERS (Stewart E. Rauch, III).
5.1 Introduction.
5.2 Hot Carriers: Physical Generation and InjectionMechanisms.
5.3 Hot Carrier Damage Mechanisms.
5.4 HC Impact to MOSFET Characteristics.
5.5 Hot Carrier Shift Models.
6 STRESS-INDUCED VOIDING (Timothy D.Sullivan).
6.1 Introduction.
6.2 Theory and Model.
6.3 Role of the Overlying Dielectric.
6.4 Summary of Voiding in Al Metallizations
6.5 Stress Voiding in Cu Interconnects.
6.6 Concluding Remarks.
7 ELECTROMIGRATION (Timothy D.Sullivan).
7.1 Introduction.
7.2 Metallization Failure.
7.3 Electromigration.
7.4 General Approach to Electromigration Reliability.
7.5 Thermal Considerations for Electromigration.
7.6 Closing Remarks.
Index.
