Transactions on High-Performance Embedded Architectures and Compilers III
Published on 23. February 2011
XIV, 299 pages
978-3-642-19448-1 (ISBN)
Description
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.
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Content
- Title Page
- Preface
- Editorial Board
- Table of Contents
- Third International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)
- Dynamic Cache Partitioning Based on the MLP of Cache Misses
- Introduction
- Prior Work in Dynamic Cache Partitioning
- MLP-Aware Dynamic Cache Partitioning
- Algorithm Overview
- MLP-Aware Stack Distance Histogram
- Obtaining Stack Distance Histograms
- Putting All Together
- Case Study
- Experimental Environment
- Simulator Configuration
- Workload Classification
- Performance Metrics
- Evaluation Results
- Performance Results
- Design Parameters
- Hardware Cost
- Scalable Algorithm to Decide Cache Partitions
- Conclusions
- References
- Cache Sensitive Code Arrangement for Virtual Machine
- Introduction
- Related Works
- Background
- XIP with NAND Flash
- KVM Internals
- Analyzing Control Flow
- Indirect Control Flow Graph
- Tracing the Locality of the Interpreter
- The Mathematical Model
- The Process of Rewriting the Virtual Machine
- Source-Level Rearrangement
- Assembly-Level Rearrangement
- Evaluation
- Evaluation Environment
- Results of Source-Level Rearrangement
- Results of Assembly-Level Rearrangement
- Conclusion
- References
- Data Layout for Cache Performance on a Multithreaded Architecture
- Introduction
- Related Work
- Simulation Environment and Benchmarks
- Independent Data Placement
- Support from Operating System or Hardware
- Analysis of Data Objects
- Object and Edge Filtering
- Building the TRGSelect Graph
- Placement Algorithm
- Independent Placement Results
- Co-ordinated Data Placement
- Merging of TRGSelect Graphs
- Coordinated Placement Results
- Exploring Other Processor and Cache Configurations
- Effects of Cache Size and Associativity
- Increasing the Number of Execution Contexts
- Effects of Cache Miss Penalty
- Conclusion
- References
- Improving Branch Prediction by Considering Affectors and Affectees Correlations
- Introduction
- Affectors and Affectees
- Definitions and Intuition
- Memory Dependences
- How to Use Affectors and Affectees for Prediction
- Experimental Framework
- Results
- Characterization of Affectors and Affectees
- GTL Results
- L-TAGE Results
- Related Work
- Conclusions and Future Work
- References
- Eighth MEDEA Workshop (Selected Papers)
- Eighth MEDEA Workshop
- Exploring the Architecture of a Stream Register-Based Snoop Filter
- Introduction
- Related Work
- Snoop Filter Architecture
- Point-to-Point Snoop Filter Interconnection
- Snoop Filter Variants
- Stream Registers
- Experimental Methodology
- Experiments and Simulation Results
- Stream Register Size
- Stream Register Update Policy
- Stream Register Clearing
- Snoop Cache Size
- The Most Effective Combination
- Conclusion
- References
- CROB: Implementing a Large Instruction Window through Compression
- Introduction
- Related Work
- Description of the Architecture
- ROB Implementation
- Compressed ROB (CROB)
- Hardware Components
- Hardware Behavior
- Early Register Release
- Experimental Results
- Simulation Methodology
- Potential Benefit of CROB
- Early Register Release
- Putting It All Together
- Conclusions
- References
- Power-Aware Dynamic Cache Partitioning for CMPs
- Introduction
- Locality Assessment
- Cache Control Mechanism
- Assumptions
- Mechanism Overview
- Way-Allocation Function
- Power Control Function
- Performance Evaluation
- Methodology
- Evaluation of Way-Allocation Function
- Evaluation of Way-Allocation with Power Control
- Evaluation of Hardware Overhead
- Conclusions
- References
- A Multithreaded Multicore System for Embedded Media Processing
- Introduction
- Multithreading
- Classification
- Selection
- Static Interleaved Multithreading
- Subset Static Interleaved Multithreading
- Register File Design
- Multithreading Comparison
- Task Scheduling
- Task Scheduling Unit
- Improvement for Multithreading
- Parallel H.264 Decoding
- Parallelization
- Tail Submits
- Evaluation
- Experimental Setup
- Performance of SSI Multithreading
- Multithreading Aware Task Scheduling
- Discussion
- Related Work
- Conclusions
- References
- Regular Papers
- Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector
- Introduction
- The Harris Interest Point Detection Algorithm
- Algorithm Description
- Implementation Details
- Optimizations and Parallelization Strategies
- Signal Processing Optimization
- DMA Related Optimizations
- Parallel Implementations
- Models Comparison
- Tile Size Influence
- Performance Analysis
- Comparison between the SPU and General Purpose Processors (GPP) with SIMD Extensions
- Discussion on Benchmarking Methodology
- Scalability Measure on the Cell Processor
- Conclusion and Future Work
- References
- Constructing Application-Specific Memory Hierarchies on FPGAs
- Introduction
- Comparison of Memory Systems on Processors and on FPGAs
- Influence of Address Complexity on Circuit Complexity
- Step-by-Step Construction of a Memory Hierarchy
- Case Study: System Integration of an IDWT
- Adding New Hardware Structures
- Inserting Buffers
- Further Integration
- Related Work
- Address Expressions
- High-Level Synthesis Tools
- Conclusions and Future Work
- References
- First Workshop on Programmability Issues for Multi-core Computers (MULTIPROG)
- autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems
- Introduction
- Related Work
- The autopin Tool
- Experimental Setup
- Benchmark
- Hardware Environment
- Thread-to-Core Pinning
- Results
- Verification of the autopin Approach
- Overhead Examination
- Conclusion and Outlook
- References
- Robust Adaptation to Available Parallelism in Transactional Memory Applications
- Introduction
- Transactional Concurrency Tuning
- Four Controller Models
- P-only Controller Model
- Evaluation of the Controller Models
- Controller Model Parameters
- Hardware and Software Platform
- Benchmarks
- Execution Time
- Resource Utilisation
- Transaction Execution Metrics
- Response Characteristics
- Limitations
- Conclusion
- References
- Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems
- Introduction
- Baseline System and Problem Statement
- Baseline Architecture
- Problem Statement
- The Intermediate Check-Point-Insertion Scheme
- Overview of the Scheme
- Implementation
- Experimental Methodology
- Experimental Results
- Potential Gains by Inserting Intermediate Checkpoints
- Micro-benchmark Performance
- Performance Gains for all Applications
- Accuracy of the Prediction Scheme
- Variation Analysis
- Related Work
- Concluding Remarks
- References
- Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies
- Introduction
- Related Work
- Motivation and the New Saving Opportunity
- Our Techniques for Instruction Cache Leakage Reduction
- Problem Formulation
- Experimental Results
- Evaluation Results
- Analysis and Evaluation of Costs
- Conclusion
- References
- Author Index
