Low Power Networks-on-Chip
1st Edition
Published on 24. September 2010
XIX, 287 pages
978-1-4419-6911-8 (ISBN)
Description
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
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Other editions
Additional editions
Cristina Silvano | Marcello Lajolo | Gianluca Palermo
Low Power Networks-on-Chip
Book
11/2014
Springer
€106.99
Shipment within 15-20 days
Cristina Silvano | Marcello Lajolo | Gianluca Palermo
Low Power Networks-on-Chip
Book
10/2010
Springer
€149.79
Shipment within 15-20 days
Content
Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.
