Low Power VLSI Design

Name: Low Power VLSI Design | Fundamentals
Brand: De Gruyter Oldenbourg
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Fundamentals

Angsuman Sarkar Swapnadip De Manash Chanda Chandan Kumar Sarkar(Author)

De Gruyter Oldenbourg (Publisher)

1st Edition

Published on 8. August 2016

XIV, 310 pages

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978-3-11-045529-8 (ISBN)

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Intro
Contents
1 Introduction to Low Power Issues in VLSI
1.1 Introduction to VLSI
1.2 Low Power IC Design beyond Sub-20 nm Technology
1.3 Issues Related to Silicon Manufacturability and Variation
1.4 Issues Related to Design Productivity
1.5 Limitation Faced by CMOS
1.6 International Technology Roadmap for Semiconductors
1.7 Different Groups of MOSFETs
1.8 Three MOS Types
1.9 Low Leakage MOSFET
1.10 Importance of Subthreshold Slope
1.11 Why Is Subthreshold Current Exponential in Nature?
1.12 Subthreshold Leakage and Voltage Limits
1.13 Importance of Subthreshold Slope in Low Power Operation
1.14 Ultralow Voltage Operation
1.15 Low Power Analog Circuit Design
1.16 Fundamental Consequence of Lowering Supply Voltage
1.17 Analog MOS Transistor Performance Parameters
Summary
References
2 Scaling and Short Channel Effects in MOSFET
2.1 MOSFET Scaling
2.2 International Technology Roadmap for Semiconductors
2.3 Gate Oxide Scaling
2.4 Gate Leakage Current
2.5 Mobility
2.6 High-k Gate Dielectrics
2.7 Key Guidelines for Selecting an Alternative Gate Dielectric
2.8 Materials
2.9 Gate Tunneling Current
2.10 Gate Length Scaling
2.11 Introduction to Short Channel Effect in MOSFET
2.11.1 Reduction of Effective Threshold Voltage
2.11.2 Drain-induced Barrier Lowering
2.11.3 Mobility Degradation and Surface Scattering
2.11.4 Surface Scattering
2.11.5 Hot Carrier Effect
2.11.6 Punch-through Effect
2.11.7 Velocity Saturation Effect
2.11.8 Increase in Off-state Leakage Current
2.12 Motivation for Present Research
2.12.1 Lightly Doped Drain Structure
2.12.2 Channel Engineering Technique
2.12.3 Gate Engineering Technique
2.12.4 Single Halo Dual Material Gate MOSFET
2.12.5 Double Halo Dual Material Gate MOSFET
2.12.6 Double Gate MOSFET
2.12.7 Dual Material Double Gate MOSFET
2.12.8 Triple Material Double Gate MOSFET
2.12.9 FinFET
2.12.10 Triple Gate MOSFET
2.12.11 Gate-all-around MOSFET
2.12.12 Surrounding Gate MOSFET
2.12.13 Silicon Nanowires
2.13 Fringing-induced Barrier Lowering
2.14 Silicon-on-insulator MOSFETs
2.15 Nonconventional Double Gate MOSFETs
2.16 Tunnel Field-effect Transistor
2.17 IMOS Device
2.18 Summary
References
3 Advanced Energy-reduced CMOS Inverter Design
3.1 Introduction
3.1.1 Transfer Characteristics of Inverter
3.1.2 Static CMOS Inverter in Super-threshold Regime
3.1.3 Introduction to Subthreshold Logic
3.1.4 Summary
References
4 Advanced Combinational Circuit Design
Introduction
4.1 Static CMOS Logic Gate Design
4.2 Complementary Properties of CMOS Logic
4.2.1 CMOS NAND Gate
4.2.2 CMOS NOR Gate
4.2.3 Some More Examples of CMOS Logic
4.2.4 XOR or Nonequivalence Gate Using CMOS Logic
4.2.5 XOR-XNOR or Equivalence Gate Using CMOS Logic
4.2.6 And-Or-Invert and Or-And-Invert Gates
4.2.7 Full Adder Circuits Using CMOS Logic
4.3 Pseudo-nMOS Gates
4.3.1 Why the Name Is Pseudo-nMOS?
4.3.2 Ratioed Logic
4.3.3 Operation of Pseudo-nMOS Inverter
4.4 Pass-transistor Logic
4.5 Complementary Pass Transistor Logic
4.6 Signal Restoring Pass Transistor Logic Design
4.7 Sizing of Transistor in CMOS Design Style
4.8 Introduction to Logical Effort
4.8.1 Definitions of Logical Effort
4.9 Delay Estimation by Logical Effort
4.10 Introduction to Transmission Gate
4.10.1 Use of CMOS TG as Switch
4.10.2 2:1 Multiplexer Using TG
4.10.3 XOR Gate Using TG
4.10.4 XNOR Gate Using TG
4.10.5 Transmission Gate Adders
4.10.6 More Examples of TG Logic
4.11 Tristate Buffer
4.12 Transmission Gates and Tristates
4.13 Implementation of Combinational Circuit Using DTMOS Logic for Ultralow Power Application
4.14 ECLR Structure
4.14.1 Power Consumption
4.14.2 Propagation Delay
References
5 Advanced Energy-reduced Sequential Circuit Design
5.1 Introduction to Sequential Circuit
5.2 Basics of Regenerative Circuits
5.3 Basic SR Flip-flop/Latch
5.3.1 NAND Gate-based Negative Logic SR Latch
5.3.2 Clocked SR Latch
5.4 Clocked JK Latch
5.4.1 Toggle Switch
5.5 Master-slave Flip-flop
5.6 D Latch
5.6.1 Positive and Negative Latch
5.6.2 Multiplexer-based Latch
5.7 Master-slave Edge-triggered Flip-flops
5.8 Timing Parameters for Sequential Circuits
5.8.1 Timing of Multiplexer-based Master-slave Flipflop
5.8.2 The Sizing Requirements for the Transmission Gates
5.9 Clock Skews due to Nonideal Clock Signal
5.10 Design and Analysis of the Flip-flops Using DTMOS Style
5.10.1 SR Latch and Flip-flop
5.10.2 JK Latch and JK Flip-flop
5.10.3 D Flip-flop
5.11 Adiabatic Flip-flop
References
6 Introduction to Memory Design
Introduction
6.1 Types of Semiconductor Memory
6.2 Memory Organization
6.3 Introduction to DRAM
6.4 One-transistor DRAM Cell
6.4.1 Write
6.4.2 Hold
6.4.3 Read
6.5 Capacitor in DRAM
6.6 Refresh Operation of DRAM
6.7 DRAM Types
6.7.1 FPM DRAMs
6.7.2 Extended Data Out DRAMs
6.7.3 Burst EDO DRAMs
6.7.4 ARAM
6.7.5 Cache DRAM
6.7.6 Enhanced DRAM (EDRAM)
6.7.7 Synchronous DRAM
6.7.8 Double Data Read DRAMs
6.7.9 Synchronous Graphic RAM
6.7.10 Enhanced Synchronous DRAMs
6.7.11 Video DRAMs
6.7.12 Window DRAMs
6.7.13 Pseudo-static RAMs
6.7.14 Rambus DRAMs
6.7.15 Multibank DRAM
6.7.16 Ferroelectric DRAM
6.8 SOI DRAM
6.8.1 Operating Principle
6.8.2 Design Considerations of SOI DRAM
6.9 Introduction to SRAM
6.10 SRAM Cell and Its Operation
6.11 SRAM Cell Failures
6.12 Performance Metrics of SRAM
6.12.1 Static Noise Margin
6.12.2 Reliability Issues of 6-T SRAM
6.13 Read-only Memory
6.14 EPROM
6.15 Electrically Erasable Programmable Read-only Memory (E2PROM)
6.16 Flash Memory
6.17 Summary
References
7 Analog Low Power VLSI Circuit Design
7.1 Analog Low Power Design: Problems with Transistor Mismatch
7.2 Mixed-signal Design with Sub-100 nm Technology
7.3 Challenges in MS Design in Sub-100 nm Space
7.3.1 Lack of Convergence of Technology
7.3.2 Digital Scaling
7.3.3 Memory Scaling
7.3.4 Analog Scaling
7.3.5 Degraded SNR
7.3.6 Degradation in Intrinsic Gain
7.3.7 Device Leakage
7.3.8 Mismatch due to Reduced Matching
7.3.9 Availability of Models
7.3.10 Passives
7.3.11 RF Scaling
7.3.12 Issues Related with Power Devices
7.4 Basics of Switched-capacitor Circuits
7.4.1 Resistor Emulation Using SC Network
7.4.2 Integrator Using SC Circuits
7.4.3 SC Integrator Sensitive to Parasitic
7.4.4 Low Power Switched-capacitor Circuit
7.5 Current Source/Sink
7.5.1 Technique to Increase Output Resistance
7.6 Low Power Current Mirror
7.6.1 Use of Current Mirrors in IC
7.6.2 Simple Current Mirror
7.6.3 Wilson Current Mirror
7.6.4 Cascode Current Mirror
7.6.5 Low Voltage Current Mirror
7.7 Fundamentals of Current/Voltage Reference
7.7.1 Another Way to Obtain Simple Bootstrap Voltage Reference Circuit with Start-up Circuit
7.8 Bandgap Voltage Reference
7.8.1 Positive TC Voltage
7.8.2 Negative TC Voltage
7.9 An Introduction to Analog Design Automation
7.9.1 Survey of Previous Analog Design Flow
7.9.2 Analog and Mixed-signal Design Process
7.9.3 Hierarchical Analog Design Methodology
7.9.4 Current Status for the Main Tasks in Analog Design Automation
7.10 Field-programmable Analog Arrays
7.11 Summary
References
Index

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Low Power VLSI Design

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