Low Power Interconnect Design
1st Edition
Published on 12. June 2015
XVII, 152 pages
978-1-4614-1323-3 (ISBN)
Description
This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
More details
Series
Language
English
Place of publication
New York
United States
Publishing group
Springer US
Target group
Professional and scholarly
Product notice
Reflowable
Illustrations
XVII, 152 p. 111 illus., 12 illus. in color.
File size
5,10 MB
ISBN-13
978-1-4614-1323-3 (9781461413233)
DOI
10.1007/978-1-4614-1323-3
Schweitzer Classification
Other editions
Additional editions
Content
Part I Basics of Interconnect Design.- Introduction to Interconnects.- CMOS Buffer.- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design.- Buffer Insertion as a Solution to Interconnect Issues.- Schmidt Trigger Approach.- Part III Bus Coding Techniques for Low Power Interconnect Design.- Bus Coding Techniques.
