Radio Frequency System Architecture and Design

Name: Radio Frequency System Architecture and Design
Brand: Artech House
Price: 139.99 EUR
Availability: OnlineOnly

John W. M. Rogers(Author)

Artech House (Publisher)

1st Edition

Published on 1. January 2013

318 pages

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978-1-60807-538-6 (ISBN)

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Intro
Radio Frequency System Architecture and Design
Contents
Preface
Chapter 1 Introduction to RF Systems Design
1.1 Introduction
1.2 What is a Radio and Why Do We Need One?
1.3 The Radio Spectrum
1.4 A Communication Device
1.5 Baseband Signal Processing Versus RFIC Design
1.6 Overview
References
Chapter 2 An Introduction to Communication Systems
2.1 A Simple Digital Communication System
2.2 Basic Modulation Schemes
2.2.1 Amplitude Shift Keying (ASK)
2.2.2 Phase Shift Keying (PSK)
2.2.3 Frequency Shift Keying (FSK)
2.2.4 Quadrature Amplitude Modulation (QAM)
2.3 Signal Models
2.3.1 Complex Lowpass Equivalent Signal Representation
2.3.2 Signal Space Diagrams
2.4 System Model
2.4.1 Symbol Map
2.4.2 Pulse-Shaping Filter
2.4.3 Modulator
2.4.4 Additive White Gaussian Noise (AWGN) Channel Model
2.4.5 Demodulator
2.4.6 Receive Filter
2.4.7 Signal Sampling
2.4.8 Decision Device
2.5 Probability of Error Analysis
2.5.1 Binary Signaling
2.5.2 M-ary Signaling
2.5.3 BER Comparison of Different Modulation Schemes
2.6 Signal Spectral Density
2.6.1 Signal Bandwidth
2.6.2 Pulse Shaping and Intersymbol Interference
2.6.3 Frequency Division Multiple Access
2.7 Wireless Channel Models
2.7.1 Signal Attenuation
2.7.2 Propagation Delay
2.7.3 Multipath Interference and Fading
2.8 Advanced Communication Techniques
2.8.1 Orthogonal Frequency Division Multiplexing
2.8.2 Multiple Antenna Systems
2.8.3 Spread Spectrum Systems
2.8.4 Error Control Coding
2.9 Summary
References
Chapter 3 Basic RF Design Concepts and Building Blocks
3.1 Introduction
3.2 Gain
3.3 Noise
3.3.1 Thermal Noise
3.3.2 Available Noise Power
3.3.3 Available Noise Power from an Antenna
3.3.4 The Concept of Noise Figure
3.3.5 Phase Noise
3.4 Linearity and Distortion in RF Circuits
3.4.1 Power Series Expansion
3.4.2 Third-Order Intercept Point
3.4.3 Second-Order Intercept Point
3.4.4 Fifth-Order Intercept Point
3.4.5 The 1-dB Compression Point
3.4.6 Relationships Between 1-dB Compression and IP3 Points
3.4.7 Broadband Measures of Linearity
3.4.8 Nonlinearity with Feedback
3.4.9 Nonlinear Systems with Memory: Volterra Series
3.5 Basic RF Building Blocks
3.5.1 Low Noise Amplifiers (LNAs)
3.5.2 Mixers
3.5.3 Filters
3.5.4 Voltage-Controlled Oscillators and Frequency Synthesizers
3.5.5 Variable Gain Amplifiers
3.5.6 Power Amplifiers
3.5.7 Phase Shifters
3.5.8 Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters
3.5.9 RF Switch
3.5.10 Antenna
References
References
Chapter 4 System-Level Architecture
4.1 Introduction
4.2 Superheterodyne Transceivers
4.3 Direct Conversion Transceivers
4.4 Offset Phase Locked Loop (PLL) Transmitters
4.5 Low IF Transceiver
4.6 Sliding IF Transceiver
4.7 An Upconversion-Downconversion Receiver Architecture
4.8 Coherent Versus Noncoherent Receivers
4.9 Image Rejecting/Sideband Suppression Architectures
4.10 An Alternative Single-Sideband Mixer
4.11 Image Rejection with Amplitude and Phase Mismatch
4.12 LO Generation
4.13 Channel Selection at RF
4.14 Transmitter Linearity Techniques
4.15 Multiple-Input Multiple-Output (MIMO) Radio Architectures
Chapter 5 System-Level Design Considerations
5.1 Introduction
5.2 The Noise Figure of Components in Series
5.3 The Linearity of Components in Series
5.4 Dynamic Range
5.5 Image Signals and Image Reject Filtering
5.6 Blockers and Blocker Filtering
5.7 The Effect of Phase Noise and LO Spurs on SNR in a Receiver
5.8 DC Offset
5.9 Second-Order Nonlinearity Issues
5.10 Automatic Gain Control Issues
5.11 Frequency Planning Issues
5.11.1 Dealing with Spurs in Frequency Planning
5.12 EVM in Transmitters Including Phase Noise, Linearity, IQ Mismatch, EVM with OFDM Waveforms, and Nonlinearity
5.13 Adjacent Channel Power
5.14 Important Considerations in Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC)
5.15 ADC and DAC Basics
References
Chapter 6 Frequency Synthesis
6.1 Introduction
6.2 Integer-N PLL Synthesizers
6.3 PLL Components
6.3.1 Voltage-Controlled Oscillators (VCOs) and Dividers
6.3.2 Phase Detectors
6.3.3 The Loop Filter
6.4 Continuous-Time Analysis for PLL Synthesizers
6.4.1 Simplified Loop Equations
6.4.2 PLL System Frequency Response and Bandwidth
6.4.3 Complete Loop Transfer Function Including C2
6.5 Discrete Time Analysis for PLL Synthesizers
6.6 Transient Behavior of PLLs
6.6.1 PLL Linear Transient Behavior
6.6.2 Nonlinear Transient Behavior
6.6.3 Various Noise Sources in PLL Synthesizers
6.6.4 In-Band and Out-of-Band Phase Noise in PLL Synthesis
6.7 Reference Feedthrough
6.8 Fractional-N Frequency Synthesizers
6.8.1 Fractional-N Synthesizer with Dual Modulus Prescaler
6.8.2 Fractional-N Synthesizer with Multimodulus Divider
6.8.3 Fractional-N Spurious Components
6.9 All-Digital Phase Locked Loops
6.9.1 The Evolution to a More Digital Architecture
6.9.2 Phase Noise Limits Due to TDC Resolution
6.9.3 Phase Noise Limits Due to DCO Resolution
6.9.4 Time-to-Digital Converter Architecture
6.9.5 The Digital Loop Filter
6.9.6 ADPLL Noise Calculations
6.9.7 Time-to-Digital Converter Circuits
References
Chapter 7 Block-Level Radio Design Examples
7.1 An IEEE 802.11n Transceiver for the 5-GHz Band
7.1.1 Baseband Signal Processing
7.1.2 RF Considerations
7.2 A Basic GPS Receiver Design
7.2.1 GPS Overview
7.2.2 RF Specification Calculations
References
About the Authors
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Radio Frequency System Architecture and Design

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