Integrated Circuit Design for High-Speed Frequency Synthesis

Name: Integrated Circuit Design for High-Speed Frequency Synthesis
Brand: Artech House
Price: 139.99 EUR
Availability: OnlineOnly

John Rogers(Author)

Artech House (Publisher)

1st Edition

Published on 1. January 2005

496 pages

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978-1-58053-983-8 (ISBN)

€139.99incl. 7% vat

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Content

Intro
Contents
Preface
1 Introduction 1
1.1 Introduction to Frequency Synthesis 1
1.2 Frequency Synthesis for Telecommunications Systems 1
1.3 Frequency Synthesis for Digital Circuit Applications 5
1.4 Frequency Synthesis for Clock and Data Recovery 8
1.5 Frequency Synthesis for Modulation and Waveform Generation 11
1.6 Overview 13
References 14
2 Synthesizer Architectures 17
2.1 Introduction 17
2.2 Integer-N PLL Synthesizers 17
2.3 Fractional-N PLL Frequency Synthesizers 18
2.3.1 Fractional-N Synthesizer with Dual-Modulus Prescaler 19
2.3.2 An Accumulator with Programmable Size 21
2.3.3 Fractional-N Synthesizer with Multimodulus Divider 23
2.3.4 Fractional-N Spurious Components 24
2.4 Delay-Locked Loops 27
2.5 Clock and Data Recovery (CDR) PLLs 29
2.6 Direct Digital Synthesizers 31
2.6.1 Direct Digital Synthesizer with Read-Only Memory Lookup Table 32
2.6.2 ROM-Less Direct Digital Synthesizer 33
2.7 Direct Analog Frequency Synthesizers 33
2.8 Hybrid Frequency Synthesizers 34
References 36
3 System-Level Overview of PLL-Based Frequency Synthesis 43
3.1 Introduction 43
3.2 PLLs (Example of a Feedback System) 43
3.3 PLL Components 44
3.3.1 VCOs and Dividers 44
3.3.2 Phase Detectors 46
3.3.3 The Loop Filter 51
3.4 Continuous-Time Analysis for PLL Synthesizers 52
3.4.1 Simplified Loop Equations 53
3.4.2 PLL System Frequency Response and Bandwidth 55
3.4.3 Complete Loop Transfer Function, Including C2 56
3.5 Discrete-Time Analysis for PLL Synthesizers 58
3.6 Transient Behavior of PLLs 61
3.6.1 Linear Transient Behavior 62
3.6.2 Nonlinear Transient Behavior 66
3.7 Phase Noise and Timing Jitter in PLL Synthesis 71
3.7.1 Various Noise Sources in PLL Synthesizers 75
3.7.2 In-Band and Out-of-Band Phase Noise in PLL Synthesis 78
References 83
4 Introduction to Digital IC Design 85
4.1 Digital Design Methodology and Flow 85
4.2 Verilog HDL 88
4.2.1 Verilog Program Structure 89
4.2.2 Verilog Data Formats 94
4.2.3 Verilog Operators 95
4.2.4 Verilog Control Constructs 95
4.2.5 Blocking and Nonblocking Assignments 97
4.2.6 Tasks and Functions 99
4.3 Behavioral and Structural Modeling 101
4.4 Combinational Digital Circuit Design 102
4.5 Sequential Digital Circuit Design 103
4.6 Digital Design Example I: A Multimodulus Divider 106
4.7 Digital Design Example II: A Programmable MASH SD Modulator 109
4.7.1 MASH SD Modulator Top-Level Structure 110
4.7.2 Fractional Accumulator with Programmable Size and Seed-Loading Capability 114
4.7.3 Reset Synchronization 116
4.7.4 Simulated Results 117
References 118
5 CMOS Logic and Current Mode Logic 119
5.1 Introduction 119
5.2 CMOS Logic Circuits 120
5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs 121
5.4 Effect of Capacitance on Slew Rate 125
5.5 Trade-Off Between Power Consumption and Speed 129
5.6 CML Combinational Circuits 132
5.7 CML Sequential Circuits 134
5.8 Master-Slave D-Flip-Flop 139
5.9 CML Circuit-Delay Analysis 142
5.10 Low-Power CML Circuits 144
5.11 CML Biasing Circuits 146
5.12 Driver Circuits 150
References 152
6 Dividers and Phase-Frequency Detectors 153
6.1 Introduction 153
6.2 Dividers 153
6.2.1 A Static Divide-by-Two Circuit 155
6.2.2 Programmable Divide-by-Two or Divide-by-Three Circuit 158
6.2.3 A 50% Duty Cycle, High-Speed, Divide-by-Three Circuit 163
6.2.4 A Multimodulus Divider 165
6.2.5 A Generic MMD Architecture 170
6.2.6 Pulse-Swallow Dividers 175
6.3 Multipliers 180
6.4 Phase Detectors 181
6.4.1 Basic Types of Phase Detectors 181
6.4.2 Circuit Implementations of PFDs 183
6.4.3 Dead Zone in PFDs 186
6.4.4 Lock-Detection Circuits
6.4.5 A Modified PFD with Aligned UP and DN Pulses
6.4.6 PFDs for CDR Applications
References
7 Charge Pumps and Loop Filters 199
7.1 Introduction 199
7.2 Charge Pumps 199
7.2.1 A Basic Charge Pump 199
7.2.2 Saturation Voltage 200
7.2.3 Current Source Output Impedance 201
7.2.4 Reference Feedthrough 203
7.2.5 Transistor Gain Considerations 206
7.2.6 Charge Pump Noise 207
7.2.7 Charge Sharing 209
7.2.8 Improving Matching Between Ip and In 209
7.2.9 Charge Pumps Compatible with CML/ECL 211
7.2.10 A Differential Charge Pump 215
7.2.11 Common-Mode Feedback for a Differential Charge Pump 217
7.2.12 Another Differential Charge Pump 217
7.2.13 Programmable Bias Schemes 218
7.3 Loop Filters 218
7.3.1 Passive Loop Filters 219
7.3.2 Active Loop Filters 222
7.3.3 LC Loop Filters 224
References 230
8 Voltage-Controlled Oscillators 233
8.1 Introduction 233
8.2 Specification of Oscillator Properties 233
8.3 LC-Based VCOs 233
8.3.1 Inductors 234
8.3.2 Varactors for Oscillator Frequency Control 238
8.4 Oscillator Analysis 241
8.4.1 Colpitts Oscillator Analysis 242
8.4.2 Negative Resistance of -Gm Oscillator 244
8.5 Amplitude of a Negative Gm Oscillator 244
8.6 Several Refinements to the -Gm Topology 245
8.7 Injection-Locked Oscillators 246
8.7.1 Phase Shift of Injection-Locked Oscillator 254
8.8 Quadrature LC Oscillators Using Injection Locking 257
8.8.1 Parallel Coupled Quadrature LC Oscillators 258
8.8.2 Series Coupled Quadrature Oscillators 263
8.8.3 Other Quadrature-Generation Techniques 263
8.9 Other Techniques to Generate Quadrature Signals 264
8.10 Phase Noise in LC Oscillators 264
8.10.1 Linear or Additive Phase Noise and Leeson's Formula 265
8.10.2 Switching Phase Noise in Cross-Coupled Pairs 269
8.11 Low-Frequency Phase Noise Upconversion Reduction Techniques 270
8.11.1 Bank Switching 270
8.11.2 gm Matching and Waveform Symmetry 272
8.11.3 Differential Varactors and Differential Tuning 273
8.12 Ring Oscillators 276
8.13 Common Inverter Circuits 281
8.14 Method for Designing a Two-Stage Ring Oscillator 284
8.15 Phase Noise and Jitter in Ring Oscillators 287
8.16 Crystal Oscillators 294
8.17 Summary: Comparison of Oscillator Performance 298
References 299
9 SD Modulation for Fractional-N Synthesis 301
9.1 Introduction 301
9.2 Basic Concepts 301
9.2.1 Quantization Noise and Oversampling Effects 301
9.2.2 Noise-Shaping Effect 306
9.2.3 An Overview of SD Modulators 308
9.2.4 First-Order SD Modulators 309
9.2.5 Second-Order SD Modulators 311
9.2.6 High-Order SD Modulators 312
9.3 SD Modulation in Fractional-N Frequency Synthesis 315
9.3.1 A First-Order SD Modulator for Fractional-N Frequency Synthesis 317
9.3.2 MASH SD Modulator 319
9.3.3 Single-Stage SD Modulators with Multiple Feedback Paths 326
9.3.4 Single-Stage SD Modulators with a Single Feedback Path 327
9.3.5 A Generic High-Order SD Modulator Topology 330
9.3.5.1 Generic SD Modulator Topology with Integrators 1/(1 - z -1 ) and Without Delay in the Loop Feedback Path 331
9.3.5.2 Generic SD Modulator Topology with Integrators z -1/(1 - z -1 ) and Without Delay in the Loop Feedback Path 334
9.3.5.3 Generic SD Modulator Topology with Integrators z -1/(1 - z -1 ) and with a Delay in the Loop Feedback Path
9.3.5.4 Generic SD Modulator Topology with Integrators 1/(1 - z -1 ) and with a Delay in the Loop Feedback Path 337
9.3.6 Modified SD Modulator with Improved High-Frequency Response 338
9.3.6.1 Single-Stage Multiple Feedforward SD Modulator (SSMF-I) 338
9.6.3.2 Single-Stage Multiple Feedforward SD Modulator (SSMF-II) 339
9.3.7 Phase Noise Due to SD Converters 342
9.3.8 Randomization by Noise-Shaped Dithering 347
9.3.9 Spur Reduction Using Precalculated Seeds 349
9.3.10 Dynamic Range 349
9.3.11 Maximal Loop Bandwidth 352
9.3.12 Optimal Parameters 354
9.3.13 Performance Comparison 355
References 356
10 Direct Digital Synthesis 359
10.1 Introduction 359
10.2 DDS Theory of Operation 360
10.3 DDS Spectral Purity 363
10.3.1 Phase Noise Due to Clock Jitter 364
10.3.2 Spurs Due to Discrete Phase Accumulation 365
10.3.3 Spurs and Quantization Noise Due to Phase Truncation 367
10.3.4 Quantization Noise Due to Finite Number of Amplitude Bits 373
10.3.5 DAC Nonlinearities and Aliased Images 374
10.3.6 Oversampling Effect 376
10.4 SD Noise Shaping in DDS 376
10.4.1 DDS Using Phase Domain SD Noise Shaping 377
10.4.2 DDS Using Frequency Domain SD Noise Shaping 379
10.4.3 ROM Size Reduction Using SD Noise Shaping 379
10.5 High-Speed ROM-Less DDS 381
10.5.1 Pipelined Accumulator 383
10.5.2 Accumulator with CLA Adders 384
10.5.3 Sine-Weighted Nonlinear DACs 388
10.5.4 Nonlinear DAC Segmentations 389
10.5.5 Nonlinear Coarse DAC 391
10.5.6 Comparison of ROM-Less DDS Performance 394
References 395
11 Direct Modulation in Frequency Synthesizers 397
11.1 Introduction
11.2 Direct Modulation in PLL Frequency Synthesizers 398
11.3 Direct Digital Modulation and Waveform Generation in a DDS 401
11.3.1 Phase Modulation 403
11.3.2 Phase Shift Keying 403
11.3.3 Frequency Modulation 407
11.3.4 Minimum Shift Keying 411
11.3.5 Step Frequency 412
11.3.6 Chirp Waveforms 412
11.3.7 Amplitude Modulation 413
11.3.8 Quadrature Amplitude Modulation 413
11.3.9 Waveform Generation 414
References 415
Appendix A: A Review of Basic Control Theory417
A.1 Introduction 417
A.2 The Continuous-Time Laplace Transform 418
A.3 The Laplace Transform and Sampling 418
A.4 System Modeling with Frequency Response 423
A.4.1 Frequency Response of Continuous Systems 423
A.4.2 Frequency Response of Sampled Systems 428
A.5 Response in the Time Domain 431
A.6 Feedback Systems 436
A.7 Steady-State Error and the System Type 440
A.8 Stability 441
A.9 Root Locus 442
References 445
Appendix B: A Review of Transistor Models
B.1 Introduction 447
B.2 The Basics of CMOS Transistors 447
B.2.1 Basic DC Biasing Characteristics 447
B.2.2 Basic CMOS Square Law Equations 449
B.2.3 The Body Effect 450
B.2.4 High-Frequency Effects 450
B.2.5 Thermal Noise 451
B.2.6 Shot Noise 452
B.2.7 1/f Noise 452
B.2.8 Gate Noise 452
B.2.9 CMOS Small-Signal Model, Including Noise 453
B.3 Bipolar Transistors 453
References 457
About the Authors 459
Index 461

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Integrated Circuit Design for High-Speed Frequency Synthesis

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