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Introduction

1.1 Phase-Lock Technique

A basic concept of a phase-locked feedback system for frequency generation was proposed in the early 1930s, but the use of a phase-locked loop (PLL) circuit for mass production began with analog television systems in the 1940s. Since then, the PLL has been one of the most critical building blocks in modern communication IC systems, covering both wireless and wireline applications.

What is the main function of the PLL? From the name and a block diagram shown in Fig. 1.1, it can be deduced that it is the loop that performs a phase lock between a reference clock and an output clock. In the coherent communication systems that use the amplitude and phase information of a signal for modulation and demodulation, interestingly, the phase-lock has not been the primary goal of the PLL in most cases. Let us look at some descriptions of the PLL in other books.

• A circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase [Best].
• A circuit that synchronizes the signal from an oscillator with a second input signal, so that they operate at the same frequency [Egan].
• When the loop is (phase) locked, the control voltage sets the average frequency of the oscillator exactly equal to the average frequency of the input signal [Gardner].
• Basically, an oscillator whose frequency is locked onto some frequency component of an input signal, which is done with a feedback control loop [Wolaver].

The first description addresses the basic function of the PLL both in phase and frequency domains. In the second or the third description, the goal of the PLL is to achieve the same frequency as the input frequency by using a phase-lock technique. In the last description, the phase lock was not even mentioned, and the PLL was simply defined as an oscillator whose frequency is locked to the input frequency. As implied by those descriptions, we can see that the primary goal of the PLL is not the phase-lock but the frequency-lock. This is because the frequency offset between an input signal and a local oscillator in the coherent receiver system is much more serious than the phase offset problem.

Figure 1.1 Accurate frequency control by a phase-lock technique.

If the main goal of the PLL is to achieve the frequency-lock, we may wonder if a frequency-locked loop (FLL) should be used instead of the PLL. The reason is that the FLL still generates a static frequency error if there exist circuit mismatches, a limited loop gain at DC, or a limited resolution in a frequency detector. To the contrary, the PLL generates a static phase error rather than the frequency error in the presence of a limited loop gain at DC or imperfect matching in a phase detector circuit. Since the frequency error fe is the derivative of the phase error ?e, the PLL always achieves a zero-frequency error even with the presence of a static phase error illustrated in Fig. 1.1. In other words, the PLL guarantees that the accuracy of an output frequency is the same as that of a source frequency based on the phase-lock technique. From that point of view, the PLL can be referred as a phase-locking loop rather than the phase-locked loop since the phase-lock is not the goal but an active method to achieve the frequency-lock. This explains why the PLL has been dominantly employed in the coherent communication system where the frequency offset between a carrier and a local oscillator is critical. When the PLL is used for frequency generation, we may regard the PLL as the oscillator circuit that generates an adaptive DC control voltage Vctr to an internal voltage-controlled oscillator (VCO) so that a stable output frequency is maintained over process-voltage-temperature (PVT) variations as depicted in Fig. 1.1.

1.2 Key Properties and Applications

In addition to the zero-frequency error, there is another important property. The PLL is the only device that performs auto-tracking band-pass filtering with high-quality factor Q and wide tunability. The high-Q band-pass filtering with wide tunability is possible since the bandwidth of a PLL can be independently set without limitation to an output frequency, while the tunability is determined by the tuning range of a VCO regardless of the PLL bandwidth. This feature is well utilized for clock-and-data recovery (CDR) systems to extract a clean clock from a noisy input data. In the CDR system, the phase-lock property is also used to define an optimum edge-of-clock position for data retiming. Besides those two properties, the inherent property of the PLL, phase-lock, makes the PLL play an important role in modern wireline communication systems. As data rate or clock frequency increases, clock de-skewing or phase synchronization has become critical to enhance the data throughput of serial I/O interfaces since the advent of the monolithic PLL implemented with complementary metal-oxide semiconductor (CMOS) technology in the late 1980s. Below is the summary of three fundamental properties of the PLL:

• Zero-frequency error
• High-Q auto-tracking BPF
• Phase synchronization

With those three features, the PLL has been employed for diverse communication systems. We briefly introduce several applications of the PLL, and some key applications will be discussed in detail in later chapters.

1.2.1 Frequency Synthesis

Since the PLL enables the zero-frequency offset between a reference clock and a feedback clock, this feature can be used to generate multiple output frequencies by adding counters in the reference clock path and the feedback clock path of the PLL. As depicted in Fig. 1.2(a), with a fixed reference frequency fref, the output frequency fout can be set by simply changing the counting values of the digital counters, that is, M and N in the reference-path and the feedback-path counters, respectively. Then, we obtain fout given by N × (fref/M) since the feedback frequency (= fout/N) must be equal to the phase-detector frequency fPD (= fref/M) after the phase-lock. Therefore, the frequency accuracy of the PLL is as good as that of the stable reference source which is typically a crystal oscillator.

1.2.2 Clock-and-Data Recovery

There are three main roles of the PLL for CDR systems. Firstly, a phase detector of the PLL directly extracts a clock information from a non-return-to-zero (NRZ) data without requiring other nonlinear circuits such as a differentiator followed by a squarer as done in traditional CDR systems. Secondly, the PLL acts as a high-Q auto-tracking band-pass filter to recover a clean clock from noisy incoming data by rejecting high-frequency jitter. Thirdly, the PLL recovers the data by re-timing the data with the extracted clean clock. The data retiming is normally performed with a D-type flip-flop (DFF). The phase-lock feature is also utilized for the data re-timing. For example, the falling edge of a recovered clock is used to trigger the DFF when the transition edge of the NRZ data is synchronized to the rising edge of the recovered clock, which gives an optimum clock position for bit slicing, i.e. data retiming as illustrated in Fig. 1.2(b).

Figure 1.2 Three key applications of the PLL: (a) frequency synthesis; (b) CDR; and (c) synchronization.

1.2.3 Synchronization

Clock jitter has become more important than ever for input/output (I/O) links in recent chip-to-chip communications as clock speed increases. In addition to the clock jitter, a clock skew between an internal clock and an external clock is a concern with high clock frequency. The delay variation due to a big clock tree in a chip significantly increases a worst-case clock skew, making available phase margin much less than expected. By having the clock tree as the part of a PLL, the clock skew variation between the external clock CKext and the internal clock CKint due to the clock tree can be minimized as illustrated in Fig. 1.2(c). Since the frequency offset is negligible in the chip-to-chip communication, a delay-locked loop (DLL) having a voltage-controlled delay line can also be used to achieve better power supply rejection and more flexible clock control than the PLL.

1.2.4 Modulation and Demodulation

In modern transceiver systems, the PLL plays an important role not only as a local oscillator but also as a frequency/phase modulator. These days, digital frequency/phase modulation based on a fractional-N PLL, as shown in Fig. 1.3(a), greatly simplifies the transmitter architecture. We will discuss how a direct-digital modulation is achieved by the PLL in Chapter 9. Figure 1.3(b) also shows two cases of an...