System-on-a-Chip Verification
Methodology and Techniques
Published on 8. May 2007
XX, 372 pages
978-0-306-46995-4 (ISBN)
Description
System-On-a-Chip Verification: Methodology and Techniques
is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for
Bluetooth
application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
- Explanation of the objective involved in performing verification after a given design step;
- Features of options available;
- When to use a particular option;
- How to select an option; and
- Limitations of the option.
More details
Other editions
Additional editions
Prakash Rashinkar | Peter Paterson | Leena Singh
System-on-a-Chip Verification
Methodology and Techniques
Book
04/2013
Springer
€171.19
Shipment within 15-20 days
Prakash Rashinkar | Peter Paterson | Leena Singh
System-on-a-Chip Verification
Methodology and Techniques
Book
12/2000
Kluwer Academic Publishers
€171.19
Shipment within 15-20 days
Content
System-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.
