
Pulse Width Modulation
Description
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This book offers a general approach to pulse width modulation techniques and multilevel inverter topologies. The multilevel inverters can be approximately compared to a sinusoidal waveform because of their increased number of direct current voltage levels, which provides an opportunity to eliminate harmonic contents and therefore allows the utilization of smaller and more reliable components. On the other side, multilevel inverters require more components than traditional inverters and that increases the overall cost of the system. The various algorithms for multilevel neutral point clamped inverter fed induction motor are proposed and implemented, and the results are analyzed. The performance of these algorithms is evaluated in terms of inverter output voltage, current waveforms and total harmonic distortion. Various basic pulse width modulation techniques, features and implementation of space vector pulse width modulation for a two-level inverter, and various multilevel inverter topologies are discussed in detail.
This book is extremely useful for undergraduate students, postgraduate students, industry people, scientists of research laboratories and especially for the research scholars who are working in the area of multilevel inverters.
Dr. Satish Kumar Peddapelli
is Assistant Professor at the Osmania University in Hyderabad, India. His areas of interest are Power Electronics, Drives, Power Converters, Multi Level Inverters and Special Machines.
Reviews / Votes
Journal of Electrical Electronics Engineering Research
International Journal of Power Electronics and Drive Systems
Bulletin of Electrical Engineering and Informatics
International Journal of Engineering and Advanced Technology
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Satish Kumar Peddapelli , Hyderabad, India
Content
- Intro
- Preface
- Acknowledgments
- Contents
- List of Tables
- List of Figures
- Nomenclature and Abbreviations
- 1 Pulse width modulation techniques
- 1.1 Pulse width modulation
- 1.2 Basic pulse width modulation techniques
- 1.2.1 Single pulse width modulation
- 1.2.2 Multiple pulse width modulation
- 1.2.3 Sinusoidal pulse width modulation
- 1.3 Advanced modulation techniques
- 1.3.1 Trapezoidal modulation
- 1.3.2 Staircase modulation
- 1.3.3 Stepped modulation
- 1.3.4 Harmonic-injected modulation
- 1.3.5 Delta modulation
- 1.3.6 Space vector pulse width modulation
- 1.4 Advantages of pulse width modulation techniques
- 1.5 Conclusions
- 2 Space vector pulse width modulation technique
- 2.1 Features of SVPWM
- 2.2 Space vector concept
- 2.2.1 Principle of SVPWM
- 2.2.2 Definition of space vector
- 2.2.3 Advantages of SVPWM
- 2.3 SVPWM for the two-level inverter
- 2.3.1 Three-phase voltage source inverter
- 2.3.2 Determination of switching states
- 2.3.3 Calculation of switching times
- 2.3.4 Optimized switching sequence
- 2.4 Conclusions
- 3 Multilevel inverter topologies
- 3.1 Diode-clamped multilevel inverter
- 3.1.1 General features
- 3.1.2 Advantages
- 3.1.3 Disadvantages
- 3.2 Flying capacitor multilevel inverter
- 3.2.1 General features
- 3.2.2 Advantages
- 3.2.3 Disadvantages
- 3.3 Cascade H-bridge multilevel inverter
- 3.3.1 Advantages
- 3.3.2 Disadvantage
- 3.4 Conclusions
- 4 Space vector pulse width modulation algorithm for the three-level inverter
- 4.1 SVPWM for the three-level inverter
- 4.1.1 Three-level inverter topology and switching states
- 4.1.2 Voltage vectors and calculation of switching times
- 4.1.3 Optimized switching sequence
- 4.2 Results and discussions
- 4.3 Conclusions
- 5 Space vector pulse width modulation for multilevel inverters using fractal approach
- 5.1 Inherent fractal structure of multilevel inverter
- 5.2 SVPWM algorithm using the fractal approach
- 5.2.1 Three-phase (a, b, c) to two-phase (d, q) transformation
- 5.2.2 Location of the reference voltage vector
- 5.2.3 Determination of nearest three voltage vectors
- 5.2.4 Triangularization algorithm
- 5.2.5 Comparison of the reference vector with the centroid
- 5.2.6 Calculation of switching times
- 5.2.7 Concept of virtual zero
- 5.3 Algorithm implementation for the three-level inverter
- 5.3.1 Determination of switching vectors
- 5.3.2 Determination of centroid
- 5.3.3 Determination of switching times
- 5.3.4 Determination of optimized switching sequence
- 5.4 Implementation of the algorithm for the five-level inverter
- 5.4.1 Determination of switching vectors
- 5.4.2 Determination of centroids
- 5.4.3 Determination of switching times
- 5.4.4 Determination of optimized switching sequence
- 5.5 Results and discussions
- 5.6 Conclusions
- 6 Qualitative space vector pulse width modulation algorithm for multilevel inverters
- 6.1 A qualitative SVPWM algorithm for multilevel inverters
- 6.2 Seven-level NPC inverter
- 6.2.1 Calculation of duty cycles
- 6.2.2 A qualitative SVPWM algorithm
- 6.2.3 Flowchart
- 6.2.4 Location of the reference vector and correction of duty cycles
- 6.3 Results and discussions
- 6.3.1 Two-level inverter
- 6.3.2 Three-level inverter
- 6.3.3 Four-level inverter
- 6.3.4 Five-level inverter
- 6.3.5 Six-level inverter
- 6.3.6 Seven-level inverter
- 6.4 Conclusions
- 7 Space vector pulse width modulation for multilevel inverters using the decomposition method
- 7.1 Seven-level inverter
- 7.2 SVPWM algorithm using the decomposition method
- 7.2.1 Basic principle of the decomposition method
- 7.2.2 First correction of the reference voltage vector
- 7.2.3 Second correction of the reference voltage vector
- 7.2.4 Third correction of the reference voltage vector
- 7.2.5 Determination of switching times
- 7.2.6 Switching sequence
- 7.3 Results and discussions
- 7.3.1 Three-level inverter
- 7.3.2 Five-level inverter
- 7.3.3 Seven-level inverter
- 7.4 Conclusions
- 8 An analytical space vector pulse width modulation method for multilevel inverters
- 8.1 Relation between three- and two-level SVPWMs
- 8.1.1 SVPWM for the two-level inverter
- 8.1.2 Switching times calculation for the three-level inverter
- 8.2 Switching states and switching sequence
- 8.2.1 Three-level inverter
- 8.2.2 Eleven-level inverter
- 8.3 Algorithm for the N-level inverter
- 8.4 Results and discussions
- 8.4.1 Three-level inverter
- 8.4.2 Five-level inverter
- 8.4.3 Seven-level inverter
- 8.4.4 Nine-level inverter
- 8.4.5 Eleven-level inverter
- 8.5 Conclusions
- References
- Appendices
- Appendix I
- Appendix II
- Appendix III
- Appendix IV
- Appendix V
- Subject Index
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