Green Communication with Field-programmable Gate Array for Sustainable Development
1st Edition
Published on 5. September 2023
254 pages
978-1-000-92983-6 (ISBN)
Description
The text discusses the designing of field-programmable gate array-based green computing circuits for efficient green communication. It will help senior undergraduate, graduate students, and academic researchers from diverse engineering domains such as electrical, electronics and communication, and computer.
Discusses hardware description language coding of green communication computing (GCC) circuits
Presents field-programmable gate arrays-based power-efficient models
Explores the integrations of universal asynchronous receiver/transmitter and field-programmable gate arrays
Covers architecture and programming tools of field-programmable gate arrays
Showcases Verilog and VHDL codes for green computing circuits such as finite impulse response filter, parity checker, and packet counter
The text discusses the designing of energy-efficient network components, using low voltage complementary metal-oxide semiconductors, high-speed transceiver logic, and stub series-terminated logic input/output standards. It showcases how to write Verilog and VHDL codes for green computing circuits including finite impulse response filter, packet counter, and universal asynchronous receiver-transmitter.
Discusses hardware description language coding of green communication computing (GCC) circuits
Presents field-programmable gate arrays-based power-efficient models
Explores the integrations of universal asynchronous receiver/transmitter and field-programmable gate arrays
Covers architecture and programming tools of field-programmable gate arrays
Showcases Verilog and VHDL codes for green computing circuits such as finite impulse response filter, parity checker, and packet counter
The text discusses the designing of energy-efficient network components, using low voltage complementary metal-oxide semiconductors, high-speed transceiver logic, and stub series-terminated logic input/output standards. It showcases how to write Verilog and VHDL codes for green computing circuits including finite impulse response filter, packet counter, and universal asynchronous receiver-transmitter.
More details
Edition
1. Auflage
Language
English
Place of publication
London
United Kingdom
Publishing group
Taylor & Francis Ltd
Target group
College/higher education
Product notice
Reflowable
Illustrations
47 Tables, black and white; 184 Line drawings, black and white; 18 Halftones, black and white; 169 Illustrations, color; 33 Illustrations, black and white
ISBN-13
978-1-000-92983-6 (9781000929836)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Bishwajeet Pandey | Keshav Kumar
Green Communication with Field-programmable Gate Array for Sustainable Development
Book
07/2025
1st Edition
CRC Press
€76.50
Shipment within 10-20 days
Bishwajeet Pandey | Keshav Kumar
Green Communication with Field-programmable Gate Array for Sustainable Development
Book
09/2023
1st Edition
CRC Press
€186.20
Shipment within 10-20 days
Persons
Keshav Kumar is currently working as an Assistant Professor at Chandigarh University, Punjab, India. He has also worked as a JRF with NIT Patna, and as an Assistant Lecturer at Chitkara University, Punjab, India. He has completed his Master of Engineering in ECE with the specialization in Hardware Security from Chitkara University, Punjab, India. He has written over 30+ research paper in the field of Hardware security, Green Communication, Low power VLSI Design, Machine learning techniques, and IoT. He also has worked with professor of 15 different countries. His area of specialization is such as Hardware security, Green Communication, Low power VLSI Design, Machine learning techniques, WSN, and IoT. He is also associated with Gyancity Research Consultancy Pvt Ltd. He is also a member of IAENG. His Google Scholar profile: ?Keshav Kumar? - ?Google Scholar?????????; His Scopus Profile: Scopus preview - Kumar, Keshav - Author details - Scopus
Prof Dr Bishwajeet Pandey is Associate Professor in Jain University, Bangalore, India. He has completed his PhD in CSE from Gran Sasso Science Institute, L'Aquila, Italy under guidance of Prof Paolo Prinetto, Politecnico Di Torino, Italy. He has worked as an Assistant Professor at Department of CSE at Birla Institute of Applied Science, India, Assistant Professor at Department of Research in Chitkara University India, Junior Research Fellow (JRF) at South Asian University and Lecturers in Indira Gandhi National Open University. He has completed Master of Technology (IIIT Gwalior) in CSE with Specialization in VLSI, Master of Computer Application, R&D Project in CDAC-Noida, India. He has authored and coauthored 150+ papers available on his Scopus Profile (https://www.scopus.com/authid/detail.uri?authorId=57203239026). He has 2000+ Citation according to his Google Scholar Profile(https://scholar.google.co.in/citations?user=UZ_8yAMAAAAJ&hl=en). He has an experience of teaching of Cyber Security, Innovation and Startup, Computer Network, Digital Logic, Logic Synthesis, Machine Learning, System Verilog and so on. His area of research interest is Green Computing, High Performance Computing, Cyber Physical System, IoT, and Cyber Security. He is in board of director of many startups of his Students e.g. Gyancity Research Consultancy Pvt Ltd.
Prof Dr Bishwajeet Pandey is Associate Professor in Jain University, Bangalore, India. He has completed his PhD in CSE from Gran Sasso Science Institute, L'Aquila, Italy under guidance of Prof Paolo Prinetto, Politecnico Di Torino, Italy. He has worked as an Assistant Professor at Department of CSE at Birla Institute of Applied Science, India, Assistant Professor at Department of Research in Chitkara University India, Junior Research Fellow (JRF) at South Asian University and Lecturers in Indira Gandhi National Open University. He has completed Master of Technology (IIIT Gwalior) in CSE with Specialization in VLSI, Master of Computer Application, R&D Project in CDAC-Noida, India. He has authored and coauthored 150+ papers available on his Scopus Profile (https://www.scopus.com/authid/detail.uri?authorId=57203239026). He has 2000+ Citation according to his Google Scholar Profile(https://scholar.google.co.in/citations?user=UZ_8yAMAAAAJ&hl=en). He has an experience of teaching of Cyber Security, Innovation and Startup, Computer Network, Digital Logic, Logic Synthesis, Machine Learning, System Verilog and so on. His area of research interest is Green Computing, High Performance Computing, Cyber Physical System, IoT, and Cyber Security. He is in board of director of many startups of his Students e.g. Gyancity Research Consultancy Pvt Ltd.
Content
Chapter 1
Introduction to Green Communication Computing (GCC)
Chapter 2
Field Programmable Gate Arrays (FPGA)
Chapter 3
HDL Coding of GCC Circuits
Chapter 4
LVCMOS based UART for GCC
Chapter 5
SSTL based UART of GCC
Chapter 6
HSTL based UART for GCC
Chapter 7
MOBILE DDR based UART for GCC
Chapter 8
LVCMOS based FIR Filter for GCC
Chapter 9
SSTL based FIR Filter of GCC
Chapter 10
HSTL based FIR Filter for GCC
Chapter 11
MOBILE DDR based FIR Filter for GCC
Chapter 12
LVCMOS based Packet Counter for GCC
Chapter 13
SSTL based Packet Counter of GCC
Chapter 14
HSTL based Packet Counter for GCC
Chapter 15
MOBILE DDR based Packet Counter for GCC
Introduction to Green Communication Computing (GCC)
Chapter 2
Field Programmable Gate Arrays (FPGA)
Chapter 3
HDL Coding of GCC Circuits
Chapter 4
LVCMOS based UART for GCC
Chapter 5
SSTL based UART of GCC
Chapter 6
HSTL based UART for GCC
Chapter 7
MOBILE DDR based UART for GCC
Chapter 8
LVCMOS based FIR Filter for GCC
Chapter 9
SSTL based FIR Filter of GCC
Chapter 10
HSTL based FIR Filter for GCC
Chapter 11
MOBILE DDR based FIR Filter for GCC
Chapter 12
LVCMOS based Packet Counter for GCC
Chapter 13
SSTL based Packet Counter of GCC
Chapter 14
HSTL based Packet Counter for GCC
Chapter 15
MOBILE DDR based Packet Counter for GCC
