Digital System Test and Testable Design

Name: Digital System Test and Testable Design | Using HDL Models and Architectures
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Using HDL Models and Architectures

Zainalabedin Navabi(Author)

Springer (Publisher)

1st Edition

Published on 10. December 2010

XVII, 435 pages

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978-1-4419-7548-5 (ISBN)

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Content

Intro
Digital System Testand Testable Design
Preface
Acknowledgments
Contents
Introduction
Chapters
Appendixes
Software and Course Materials
Chapter 1: Basics of Test and Role of HDLs
1.1 Design and Test
1.1.1 RTL Design Process
1.1.1.1 RTL Simulation
1.1.1.2 RT Level Synthesis
1.1.1.3 Physical Layout
1.1.1.4 Chip Manufacturing
1.1.2 Postmanufacturing Test
1.1.2.1 Device and Its Test Data
1.1.2.2 Testers
1.1.2.3 Using Test Results
1.1.2.4 Types of Tests
1.2 Test Concerns
1.2.1 Test Methods
1.2.1.1 Fault Model
1.2.1.2 Fault Reduction
1.2.1.3 Fault Simulation
1.2.1.4 Testability Measurement
1.2.1.5 Test Generation
1.2.1.6 Test Compaction
1.2.2 Testability Methods
1.2.2.1 Ad Hoc Testability
1.2.2.2 Scan Insertion
1.2.2.3 Boundary Scan
1.2.2.4 Built-in Self-test
1.2.3 Testing Methods
1.2.4 Cost of Test
1.2.4.1 Rule of 10
1.2.4.2 Chip Testing
1.3 HDLs in Digital System Test
1.3.1 Hardware Modeling
1.3.2 Developing Test Methods
1.3.3 Virtual Testers
1.3.4 Testability Hardware Evaluation
1.3.5 Protocol Aware ATE
1.4 ATE Architecture and Instrumentation1
1.4.1 Digital Stimulus and Measure Instruments
1.4.2 DC Instrumentation
1.4.3 AC Instrumentation
1.4.4 RF Instrumentation
1.4.5 ATE
1.5 Summary
References
Chapter 2: Verilog HDL for Design and Test
2.1 Motivations of Using HDLs for Developing Test Methods
2.2 Using Verilog in Design
2.2.1 Using Verilog for Simulation
2.2.2 Using Verilog for Synthesis
2.2.2.1 Postsynthesis Simulation
2.3 Using Verilog in Test
2.3.1 Good Circuit Analysis
2.3.2 Fault List Compilation and Testability Analysis
2.3.3 Fault Simulation
2.3.4 Test Generation
2.3.5 Testability Hardware Design
2.4 Basic Structures of Verilog
2.4.1 Modules, Ports, Wires, and Variables
2.4.2 Levels of Abstraction
2.4.3 Logic Value System
2.5 Combinational Circuits
2.5.1 Transistor-level Description
2.5.2 Gate-level Description
2.5.3 Equation-level Description
2.5.4 Procedural Level Description
2.5.4.1 Multiplexer Example
2.5.4.2 Procedural ALU Example
2.5.5 Instantiating Other Modules
2.5.5.1 ALU Example Using Adder
2.5.5.2 Iterative Instantiation
2.6 Sequential Circuits
2.6.1 Registers and Shift Registers
2.6.2 State Machine Coding
2.6.2.1 Residue-5 Divider
2.6.2.2 The Moore Implementation of Residue-5 in Verilog
2.6.2.3 Huffman Coding Style
2.7 A Complete Example (Adding Machine)
2.7.1 Control/Data Partitioning
2.7.2 Adding Machine Specification
2.7.3 CPU Implementation
2.7.3.1 Datapath Design
2.7.3.2 Controller Design
2.7.3.3 Datapath HDL Description
2.7.3.4 Controller HDL Description
2.7.3.5 The Complete HDL Design
2.8 Testbench Techniques
2.8.1 Testbench Techniques
2.8.2 A Simple Combinational Testbench
2.8.3 A Simple Sequential Testbench
2.8.4 Limiting Data Sets
2.8.5 Synchronized Data and Response Handling
2.8.6 Random Time Intervals
2.8.7 Text IO
2.8.8 Simulation Code Coverage
2.9 PLI Basics
2.9.1 Access Routines
2.9.2 Steps for HDL/PLI Implementation
2.9.3 Fault Injection in the HDL/PLI Environment
2.10 Summary
References
Chapter 3: Fault and Defect Modeling
3.1 Fault Modeling
3.1.1 Fault Abstraction
3.1.2 Functional Faults
3.1.3 Structural Faults
3.2 Structural Gate Level Faults
3.2.1 Recognizing Faults
3.2.2 Stuck-open Faults
3.2.3 Stuck-at-0 Faults
3.2.4 Stuck-at-1 Faults
3.2.5 Bridging Faults
3.2.5.1 AND-bridging Faults
3.2.5.2 OR-bridging Faults
3.2.6 State-dependent Faults
3.2.7 Multiple Faults
3.2.8 Single Stuck-at Structural Faults
3.2.8.1 Stuck-at Faults
3.2.8.2 Single Fault
3.2.9 Detecting Single Stuck-at Faults
3.3 Issues Related to Gate Level Faults
3.3.1 Detecting Bridging Faults
3.3.2 Undetectable Faults
3.3.3 Redundant Faults
3.4 Fault Collapsing
3.4.1 Indistinguishable Faults
3.4.2 Equivalent Single Stuck-at Faults
3.4.3 Gate-oriented Fault Collapsing
3.4.3.1 Gate Faults
3.4.3.2 Gate-oriented Fault Collapsing Procedure
3.4.4 Line-oriented Fault Collapsing
3.4.5 Problem with Reconvergent Fanouts
3.4.6 Dominance Fault Collapsing
3.4.6.1 Dominance Principles
3.4.6.2 Dominance in Fanout-free Circuits
3.5 Fault Collapsing in Verilog
3.5.1 Verilog Testbench for Fault Collapsing
3.5.2 PLI Implementation of Fault Collapsing
3.6 Summary
References
Chapter 4: Fault Simulation Applications and Methods
4.1 Fault Simulation
4.1.1 Gate-level Fault Simulation
4.1.2 Fault Simulation Requirements
4.1.2.1 Gate-level Simulation
4.1.2.2 Behavioral Simulation
4.1.2.3 Reading Data Files
4.1.2.4 Fault Injection Capability
4.1.2.5 Writing Report Files
4.1.3 An HDL Environment
4.1.3.1 Input Files and Information
4.1.3.2 Fault Injection
4.1.3.3 Performing Fault Simulation
4.1.4 Sequential Circuit Fault Simulation
4.1.5 Fault Dropping
4.1.6 Related Terminologies
4.1.6.1 Fault Activation
4.1.6.2 Fault Propagation
4.1.6.3 Fault Detection
4.1.6.4 Fault Blocking
4.2 Fault Simulation Applications
4.2.1 Fault Coverage
4.2.1.1 Fault Coverage Procedure
4.2.1.2 HDL-based Fault Coverage
4.2.1.3 Sequential Circuit Fault Coverage
4.2.2 Fault Simulation in Test Generation
4.2.2.1 Test Refinement
4.2.2.2 Random Test Generation
4.2.2.3 Fault-oriented Test Generation
4.2.3 Fault Dictionary Creation
4.2.3.1 Fault Dictionary
4.2.3.2 Generating a Fault Dictionary
4.2.3.3 Sequential Circuit Fault Dictionary
4.2.3.4 Using Fault Dictionaries
4.3 Fault Simulation Technologies
4.3.1 Serial Fault Simulation
4.3.2 Parallel Fault Simulation
4.3.2.1 Parallel Fault Simulation Algorithm
4.3.2.2 Verilog Implementation
4.3.2.3 Comparing Parallel Fault Simulation
4.3.3 Concurrent Fault Simulation
4.3.3.1 Concurrent Fault Simulation Algorithm
4.3.3.2 Implementing Concurrent Fault Simulation
4.3.3.3 Comparing Concurrent Fault Simulation
4.3.4 Deductive Fault Simulation
4.3.4.1 Deductive Fault Simulation Algorithm
4.3.4.2 Gate Fault List Propagation
4.3.4.3 Deductive Fault Simulation Example
4.3.5 Comparison of Deductive Fault Simulation
4.3.6 Critical Path Tracing Fault Simulation
4.3.6.1 Basic CPT Implementation
4.3.6.2 Reconvergent Fanouts in CPT
4.3.6.3 CPT Example
4.3.6.4 Comparing CPT
4.3.7 Differential Fault Simulation
4.4 Summary
References
Chapter 5: Test Pattern Generation Methods and Algorithms
5.1 Test Generation Basics
5.11 Boolean Difference
5.1.2 Test Generation Process
5.1.2.1 Deterministic Search
5.1.2.2 Random Search
5.1.2.3 Methods and Algorithms
5.1.3 Fault and Tests
5.1.3.1 Fault-oriented Test Generation
5.1.3.2 Fault Independent Test Generation
5.1.3.3 Random Test Generation
5.1.3.4 Unspecified Inputs
5.1.4 Terminologies and Definitions
5.2 Controllability and Observability
5.2.1 Controllability
5.2.2 Observability
5.2.3 Probability-based Controllability and Observability
5.2.3.1 Circuits without Reconvergent Fanout
5.2.3.2 Reconvergent Fanouts
5.2.3.3 Detection Probability
5.2.3.4 Verilog Testbench
5.2.4 SCOAP Controllability and Observability
5.2.4.1 SCOAP Combinational Parameters
5.2.4.2 SCOAP Combinational Examples
5.2.4.3 Verilog Testbench for SCOAP Parameter Calculations
5.2.4.4 SCOAP Sequential Parameters
5.2.5 Distances Based
5.3 Random Test Generation
5.3.1 Limiting Number of Random Tests
5.3.1.1 Estimating Hardest Detection
5.3.1.2 Detection Probability
5.3.2 Combinational Circuit RTG
5.3.2.1 Fixed Expected Coverage per Test
5.3.2.2 Adjustable Expected Coverage per Test
5.3.2.3 Precalculated Expected Coverage per Test
5.3.3 Sequential Circuit RTG
5.4 Summary
References
Chapter 6: Deterministic Test Generation Algorithms
6.1 Deterministic Test Generation Methods
6.1.1 Two-phase Test Generation
6.1.2 Fault-oriented TG Basics
6.1.2.1 Basic TG Procedure
6.1.2.2 A More Formal Approach to TG
6.1.2.3 Multiple Sensitized Paths
6.1.3 The D-Algorithm
6.1.3.1 Primitive Cubes
6.1.3.2 Propagation D-Cubes
6.1.3.3 J-Frontier
6.1.3.4 D-Frontier
6.1.3.5 D-Algorithm Procedure
6.1.3.6 Simplified D-Algorithm
6.1.4 PODEM (Path-oriented Test Generation)
6.1.4.1 Basic PODEM
6.1.4.2 A Smarter PODEM
6.1.5 Other Deterministic Fault-oriented TG Methods
6.1.5.1 Fan
6.1.5.2 Socrates
6.1.6 Fault-independent Test Generation
6.2 Sequential Circuit Test Generation
6.3Test Data Compaction
6.3.1 Forms of Test Compaction
6.3.2 Test Compatibility
6.3.2.1 Test Vector Compatibility
6.3.2.2 Test Vector Reordering
6.3.2.3 Test Set Compatibility
6.3.3 Static Compaction
6.3.3.1 Static Combinational Compaction
6.3.3.2 Static Sequential Compaction
6.3.4 Dynamic Compaction
6.4 Summary
References
Chapter 7: Design for Test by Means of Scan
7.1 Making Circuits Testable
7.1.1 Tradeoffs
7.1.2 Testing Sequential Circuits
7.1.2.1 Sequential Circuit Huffman Model
7.1.2.2 Unfolding Sequential Model
7.1.3 Testability of Combinational Circuits
7.2 Testability Insertion
7.2.1 Improving Observability
7.2.2 Improving Controllability
7.2.3 Sharing Observability Pins
7.2.4 Sharing Control Pins
7.2.5 Reducing Select Inputs
7.2.6 Simultaneous Control and Observation
7.2.6.1 Simultaneous Control of Test Points
7.2.6.2 Simultaneous Observation of Test Points
7.2.6.3 Isolated Serial Scan
7.3 Full Scan DFT Technique
7.3.1 Full Scan Insertion
7.3.1.1 Scan Register
7.3.1.2 Test Procedure
7.3.2 Flip-flop Structures
7.3.2.1 Latches and Flip-flop
7.3.2.2 Multiplexed Test Data
7.3.2.3 Dual Clocking
7.3.2.4 Two-port Flip-flops
7.3.3 Full Scan Design and Test
7.3.3.1 Design and Design Validation
7.3.3.2 Synthesis and Netlist Generation
7.3.3.3 Unfolding
7.3.3.4 Combinational TPG
7.3.3.5 Scan Insertion
7.3.3.6 Developing a Virtual Tester
7.3.3.7 Test Set Verification
7.4 Scan Architectures
7.4.1 Full Scan Design
7.4.2 Shadow Register DFT
7.4.2.1 Shadow Architecture
7.4.2.2 Shadow Test Procedure
7.4.2.3 Shadow Versus Full Scan
7.4.3 Partial Scan Methods
7.4.3.1 A Partial Scan Architecture
7.4.3.2 Partial Scan Test Procedure
7.4.3.3 Partial Scan Versus Full Scan
7.4.4 Multiple Scan Design
7.4.4.1 Multiple Scan Architecture
7.4.4.2 Multiple Scan Test Procedure
7.4.4.3 Compared with Full Scan
7.4.5 Other Scan Designs
7.5 RT Level Scan Design
7.5.1 RTL Design Full Scan
7.5.2 RTL Design Multiple Scan
7.5.3 Scan Designs for RTL
7.6 Summary
References
Chapter 8: Standard IEEE Test Access Methods
8.1 Boundary Scan Basics
8.2 Boundary Scan Architecture
8.2.1 Test Access Port
8.2.2 BS-1149.1 Registers
8.2.2.1 Instruction Register
8.2.2.2 Data Registers
8.2.3 TAP Controller
8.2.4 The Decoder Unit
8.2.5 Select and O ther Units
8.3 Boundary Scan Test Instructions
8.3.1 Mandatory Instructions
8.3.1.1 Bypass Instruction
8.3.1.2 Sample Instruction
8.3.1.3 Preload Instruction
8.3.1.4 Extest Instructions
8.3.1.5 Intest Instruction
8.4 Board Level Scan Chain Structure
8.4.1 One Serial Scan Chain
8.4.2 Multiple-scan Chain with One Control Test Port
8.4.3 Multiple-scan Chains with One TDI, TDO but Multiple TMS
8.4.4 Multiple-scan Chain, Multiple Access Port
8.5 RT Level Boundary Scan
8.5.1 Inserting Boundary Scan Test Hardware for CUT
8.5.1.1 Instruction Register
8.5.1.2 Decoder Unit
8.5.1.3 Boundary Scan Register
8.5.1.4 Testable Design
8.5.2 Two Module Test Case
8.5.3 Virtual Boundary Scan Tester
8.5.3.1 Boundary Scan Driver Module
8.5.3.2 IO Driver Module
8.6 Boundary Scan Description Language
8.7 Summary
References
Chapter 9: Logic Built-in Self-test
9.1 BIST Basics
9.1.1 Memory-based BIST
9.1.1.1 Providing Test Data
9.1.1.2 Test Response Analysis
9.1.2 BIST Effectiveness
9.1.3 BIST Types
9.1.3.1 Offline BIST
9.1.3.2 Online BIST
9.1.3.3 Hybrid BIST
9.1.3.4 Concurrent BIST
9.1.4 Designing a BIST
9.1.4.1 Architecture Design
9.1.4.2 Designing TPGs
9.1.4.3 Designing ORAs
9.1.4.4 BIST Procedure
9.2 Test Pattern Generation
9.2.1 Engaging TPGs
9.2.2 Exhaustive Counters
9.2.3 Ring Counters
9.2.4 Twisted Ring Counter
9.2.5 Linear Feedback Shift Register
9.2.5.1 LFSR Characteristic Equation
9.2.5.2 Standard LFSR
9.2.5.3 Period of LFSR
9.2.5.4 Modular LFSR
9.2.5.5 LFSR with Serial Input
9.2.5.6 Configurable LFSR
9.2.5.7 Weighted LFSR
9.3 Output Response Analysis
9.3.1 Engaging ORAs
9.3.2 One's Counter
9.3.3 Transition Counter
9.3.4 Parity Checking
9.3.5 Serial LFSRs (SISR)
9.3.6 Parallel Signature Analysis
9.4 BIST Architectures
9.4.1 BIST-related Terminologies
9.4.1.1 TPGs and ORAs
9.4.1.2 Test Cycles, Round, and Sessions
9.4.2 A Centralized and Separate Board-level BIST Architecture (CSBL)
9.4.2.1 CSBL Hardware
9.4.2.2 CSBL Test Process
9.4.2.3 CSBL Features
9.4.3 Built-in Evaluation and Self-test (BEST)
9.4.4 Random Test Socket (RTS)
9.4.4.1 RTS Hardware
9.4.4.2 RTS Test Process
9.4.4.3 RTS Features and Improvements
9.4.5 LSSD On-chip Self Test
9.4.5.1 LOCST Architecture
9.4.5.2 LOCST Test Process
9.4.5.3 LOCST Features
9.4.6 Self-testing Using MISR and SRSG
9.4.6.1 STUMPS Structure
9.4.6.2 STUMPS Test Process
9.4.6.3 STUMPS Features
9.4.7 Concurrent BIST
9.4.7.1 CBIST Structure and Operation
9.4.8 BILBO
9.4.8.1 BILBO Architecture
9.4.8.2 BILBO Test Process
9.4.9 Enhancing Coverage
9.5 RT Level BIST Design
9.5.1 CUT Design, Simulation, and Synthesis
9.5.2 RTS BIST Insertion
9.5.2.1 Scan Insertion in netlist
9.5.2.2 Adding BIST Hardware
9.5.2.3 Design of the BIST Controller
9.5.2.4 BISTed CUT Model
9.5.3 Configuring the RTS BIST
9.5.3.1 Acceptable Configurations
9.5.3.2 Good Signatures
9.5.3.3 Evaluating Configurations by Simulation
9.5.4 Incorporating Configurations in BIST
9.5.5 Design of STUMPS
9.5.5.1 Inserting Scan Registers
9.5.5.2 Adding BIST Components
9.5.5.3 STUMPS Configuration
9.5.6 RTS and STUMPS Results
9.6 Summary
References
Chapter 10: Test Compression
10.1 Test Data Compression
10.2 Compression Methods
10.2.1 Code-based Schemes
10.2.1.1 Huffman Codes
10.2.1.2 Dictionary-based Codes
10.2.1.3 Run-length Codes
10.2.1.4 Golomb Codes
10.2.2 Scan-based Schemes
10.2.2.1 Broadcast Scan
10.2.2.2 Illinois Scan
10.2.2.3 Multiple-input Broadcast Scan
10.2.2.4 Other Methods
10.3 Decompression Methods
10.3.1 Decompression Hardware Architecture
10.3.2 Cyclical Scan Chain
10.3.3 Code-based Decompression
10.3.3.1 Huffman
10.3.3.2 Dictionary-based
10.3.3.3 Run-length
10.3.3.4 Golomb
10.3.4 Scan-Based Decompression
10.4 Summary
References
Chapter 11: Memory Testing by Means of Memory BIST
11.1 Memory Testing
11.2 Memory Structure
11.3 Memory Fault Model
11.3.1 Stuck-at Faults
11.3.2 Transition Faults
11.3.3 Coupling Faults
11.3.4 Bridging and State CFs
11.4 Functional Test Procedures
11.4.1 March Test Algorithms
11.4.2 March C- Algorithm
11.4.3 MATS+ Algorithm
11.4.4 Other March Tests
11.5 MBIST Methods
11.5.1 Simple March MBIST
11.5.1.1 Simple March MBIST Architecture
11.5.1.2 Test Session
11.5.1.3 Simple March BIST Controller
11.5.1.4 Simple March BIST Structure
11.5.1.5 BIST Tester
11.5.2 March C- MBIST
11.5.2.1 March C- BIST Counter-sequencer
11.5.2.2 Decoder
11.5.3 Disturb MBIST
11.5.3.1 Disturb BIST Walking-0
11.5.3.2 Disturb BIST Structure
11.6 Summary
References
Appendix A Using HDLs for Protocol Aware ATE1
Appendix B Gate Components for PLI Test Applications
Appendix C Programming Language Interface Test Utilities
Appendix D IEEE Std. 1149.1 Boundary Scan Verilog Description
Appendix E Boundary Scan IEEE std. 1149.1 Virtual Tester
Appendix F Generating Netlist by Register Transfer LevelSynthesis (NetlistGen)
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