Computer Architecture
Complexity and Correctness
Published on 11. November 2013
XIII, 553 pages
978-3-662-04267-0 (ISBN)
Description
Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design.
Reviews / Votes
"The book is highly interesting to computer scientists . . It is very well written, although compact and for the specialist, or for a reader with a deep interest in the details of a RISC machine. . So this book can be recommended as the text for advanced, graduate-level hardware classes since after have worked through it the reader will be best prepared for starting a job in the hardware industry right away." (Gottfried Vossen, zbMATH 0966.68023, 2022)More details
Other editions
Additional editions
Book
12/2010
Springer
€53.49
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Book
05/2000
Springer
€53.49
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Content
1 Introduction.- 2 Basics.- 3 A Sequential DLX Design.- 4 Basic Pipelining.- 5 Interrupt Handling.- 6 Memory System Design.- 7 IEEE Floating Point Standard and Theory of Rounding.- 8 Floating Point Algorithms and Data Paths.- 9 Pipelined DLX Machine with Floating Point Core.- A DLX Instruction Set Architecture.- A.1 DLX Fixed-Point Core: FXU.- A.1.1 Instruction Formats.- A.1.2 Instruction Set Coding.- A.2 Floating-Point Extension.- A.2.1 FPU Register Set.- A.2.2 FPU Instruction Set.- B Specification of the FDLX Design.- B.1 RTL Instructions of the FDLX.- B.1.l Stage IF.- B.1.2 Stage ID.- B.1.3 Stage EX.- B.1.4 Stage M.- B.1.5 Stage WB.- B.2 Control Automata of the FDLX Design.- B.2.1 Automaton Controlling Stage ID.- B.2.2 Precomputed Control.
