Engineer's Guide to Automated Testing of High-Speed Interfaces

Name: Engineer's Guide to Automated Testing of High-Speed Interfaces
Brand: Artech House
Price: 118.99 EUR
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Jose Moreira(Author)

Artech House (Publisher)

1st Edition

Published on 1. January 2010

588 pages

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978-1-60783-984-2 (ISBN)

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An Engineer's Guide to Automated Testing of High-Speed Interfaces
Contents
Preface
Acknowledgments
1 Introduction
1.1 Characterization and Design Verification
1.2 Production Testing
1.3 Accuracy and Correlation
1.4 The ATE Test Fixture
1.5 The Future
References
2 High-Speed Digital BasicsThis
2.1 High-Speed Digital Signaling
2.1.1 Out-of-Band Signaling
2.1.2 Data Eye Diagram
2.1.3 Differential Signaling
2.1.4 Transmission Line Termination
2.2 Time and Frequency Domains
2.2.1 The Concept of Bandwidth and Its Pitfalls
2.3 Bit Error Rate
2.4 Jitter
2.4.1 Jitter Histogram
2.4.2 Jitter Categorization
2.4.3 Amplitude Noise and Conversion to Timing Jitter
2.4.4 Jitter in the Frequency Domain
2.5 Classification of High-Speed I/O Interfaces
2.6 Hardware Building Blocks and Concepts
2.6.1 Phase Locked Loop (PLL)
2.6.2 Delay Locked Loop (DLL)
2.6.3 Clock and Data Recovery (CDR)
2.6.4 Pre-Emphasis/De-Emphasis and Equalization
References
3 High-Speed Interface Standards
3.1 PCI Express
3.1.1 Application Areas
3.1.2 PCI Express Fundamentals
3.1.3 PCI Express Details
3.1.4 PCI Express Protocol
3.1.5 Electrical Specifications
3.1.6 ATE Test Requirements
3.1.7 Test Support
3.1.8 Test Challenges
3.2 HyperTransport
3.2.1 Application Areas
3.2.2 HyperTransport Protocol
3.2.2.1 Data Link Layer
3.2.2.2 Physical Layer
3.2.3 Electrical Specifications
3.2.4 Test Support
3.2.5 Test Requirements
3.2.6 Test Challenges
3.3 XDR DRAM
3.3.1 Application Areas
3.3.2 XDR Fundamentals
3.3.3 XDR DRAM Details
3.3.4 XDR Protocol
3.3.5 Electrical Specifications
3.3.6 ATE Test Requirements
3.3.7 Test Support
3.3.8 Test Challenges
3.4 GDDR SDRAM
3.4.1 Application Areas
3.4.2 GDDR Fundamentals
3.4.3 GDDR5 Details
3.4.4 GDDR5 Protocol
3.4.5 Electrical Specifications
3.4.6 ATE Test Requirements
3.4.7 Test Support
3.4.8 Test Challenges
3.5 Other High-Speed Digital Interface Standards
References
4 ATE Instrumentation for DigitalApplications
4.1 Digital Pin Electronics ATE Card
4.1.1 CDR and Phase Tracking
4.1.2 Equalization
4.1.3 Time Interval Analyzer or Time Stamper
4.1.4 Timing Jitter Injection
4.1.5 Amplitude Noise and Common Mode Voltage Injection
4.1.6 Bidirectional and Simultaneous Bidirectional Support
4.1.7 Protocol Engine
4.1.8 ATE Loopback Path
4.1.9 Parametric Measurements
4.2 Sampler/Digitizer ATE Card
4.2.1 Aliasing
4.2.2 Digitizer
4.2.3 Sampler
4.3 Parametric Measurements with Sampled Data
4.3.1 Undersampling of High-Speed I/O Signals
4.3.2 Coherency Equation
4.3.3 Capturing Digital Waveforms
4.3.4 Special Considerations for Coherent Sampling with Digital ATE Channels
4.4 Power Supplies
References
5 Tests and Measurements
5.1 Bit and Pattern Alignment
5.1.1 Bit Alignment
5.1.2 Pattern Alignment
5.2 Functional Test
5.3 Shmoo Tests
5.4 Fundamental Driver Tests
5.4.1 Rise/Fall Time
5.4.2 Data Eye Diagram
5.4.3 BER Bathtub Curve
5.4.4 Skew
5.4.5 Pre-Emphasis and De-Emphasis Measurement
5.5 Driver Jitter Tests
5.5.1 Jitter Histogram
5.5.2 RMS Jitter
5.5.3 Peak-to-Peak Jitter
5.5.4 Measuring the Jitter Spectrum
5.5.5 Random and Deterministic Jitter Separation
5.5.6 Measuring the Data Dependent Jitter
5.5.7 Jitter Measurement Correlation
5.5.8 Driver Amplitude Noise
5.6 Fundamental Receiver Tests
5.6.1 Setup and Hold
5.6.2 Receiver Sensitivity
5.7 Receiver Jitter Tolerance
5.7.1 Random Jitter Tolerance
5.7.2 Sinusoidal Jitter Tolerance
5.7.3 DDJ Jitter Tolerance
5.7.4 Testing the Receiver Equalizer
5.8 PLL Characterization
5.8.1 Jitter Transfer
5.8.2 Frequency Offset
5.8.3 Spread Spectrum Clocking
5.9 Other Tests
5.9.1 Impedance Tests
5.9.2 Return Loss
5.10 Measurement Errors
References
6 Production Testing
6.1 Golden Device
6.2 System Level Test
6.3 Instrument-Based Testing: At-Speed ATE
6.3.1 Physical Implementation
6.3.2 Parametric Testing
6.4 Instrument-Based Testing: Low-Speed ATE
6.4.1 Double Data Clocking
6.4.2 Channel Multiplexing
6.4.3 Near-End Loopback Testing
6.5 Instrument-Based Testing: Bench Instrumentation
6.6 Active Test Fixture
6.7 Multisite Testing
6.7.1 Driver Sharing for Multisite Applications
References
7 Support Instrumentation
7.1 Oscilloscopes
7.1.1 Real-Time Oscilloscopes
7.1.2 Equivalent-Time Sampling Oscilloscopes
7.2 Bit Error Rate Tester
7.3 Time Interval Analyzer
7.4 Spectrum Analyzer
7.5 Vector Network Analyzer
7.6 Arbitrary Waveform and Function Generators
7.7 Noise Generators
7.8 Sinusoidal Clock Sources
7.9 Connecting Bench Instrumentation to an ATE System
7.9.1 Signal Integrity
7.9.2 Synchronization
7.9.3 External Reference Clock Impact on Jitter Measurements
7.10 Coaxial Cables and Connectors
7.10.1 Coaxial Cables
7.10.2 Coaxial Connectors
7.11 Accessories
7.11.1 Power Splitters and Power Dividers/Combiners
7.11.2 Attenuators, Blocking Capacitors, and Terminations
7.11.3 Pick-Off T
7.11.4 Delay Lines
7.11.5 Probes
7.11.6 Balun
7.11.7 Rise Time Converters
References
8 Test Fixture Design
8.1 Test Fixtures
8.2 High-Speed Design Effects
8.2.1 Reflections Due to Impedance Mismatches
8.2.2 Conductor Losses
8.2.3 Dielectric Losses
8.2.4 Crosstalk
8.3 Impedance Controlled Routing
8.3.1 Microstrip and Striplines
8.3.2 Differential Routing
8.4 Via Transitions
8.4.1 Interlayer Vias
8.4.2 Pogo Pin Vias
8.5 DUT BGA Ballout
8.6 Sockets
8.6.1 Socket Electrical Characterization
8.7 Relays
8.8 Bidirectional Layout
8.9 Wafer Probing
8.10 Stack-Up
8.11 Power Distribution Network
8.11.1 Power Planes
8.11.2 Decoupling Capacitors
8.11.3 Socket Inductance
8.11.4 Power Distribution Network Design
8.11.5 Power Distribution Network Simulation
References
9 Advanced ATE Topics
9.1 ATE Specifications and Calibration
9.1.1 Accuracy and Resolution
9.1.2 Understanding OTA and EPA
9.1.3 Linearity and Edge Placement Accuracy
9.1.4 Calibration
9.2 Multiplexing of ATE Channels
9.3 Focus Calibration
9.3.1 Skew Calibration
9.3.2 Data Eye Height Calibration
9.3.3 Jitter Injection
9.3.4 Data Eye Profile
9.4 Testing of High-Speed Bidirectional Interfaces with a Dual Transmission Line Approach
9.5 Including the DUT Receiver Data Recovery in Driver Tests
9.6 Protocol Awareness and Protocol-Based Testing
9.7 Testing Multilevel Interfaces with Standard Digital ATE Pin Electronics
9.8 Signal Path Characterization and Compensation
9.8.1 Signal Path Loss Compensation: De-Embedding
9.8.2 Characterization in the Frequency Domain
9.8.3 Signal Path Loss Compensation: Equalization
9.9 ATE DC Level Adjustments
9.9.1 Correction of Force Levels for DUT Input Pins
9.9.2 Correction of Levels for DUT Output Pins
References
A Introduction to the Gaussian Distribution and Analytical Computation of the BER
A.1 The Gaussian Distribution
A.2 Computation of the BER for a System with Only Gaussian Random Jitter
A.3 Computation of the a(BER) Value
A.4 Properties of the Error Function erf(x) and Complementary Error Function erfc(x)
References
B The Dual Dirac Model and RJ/DJ Separation
B.1 The Dual Dirac Jitter Model
B.2 RJ/DJ Separation with the Q-Factor Algorithm
References
C Pseudo-Random Bit Sequences and Other Data Patterns
C.1 Pseudo-Random Bit Sequences
C.2 Pseudo-Random Word Sequences
C.3 Other Important Patterns
References
D Coding, Scrambling, Disparity,and CRC
D.1 Disparity
D.2 8B/10B Coding
D.3 Scrambling
D.4 Error Detection
D.4.1 Parity Bits
D.4.2 Checksums
References
E Time Domain Reflectometry andTime Domain Transmission(TDR/TDT)
E.1 TDR
E.1.1 Measuring the Impedance of a Trace with a TDR
E.1.2 Measuring the Round-Trip Delay of a Signal Trace
E.1.3 Measuring Discontinuities on a Signal Path with a TDR
E.1.4 Measuring the Return Loss with a TDR
E.2 TDT
E.2.1 Measuring the Step Response
E.2.2 Measuring the Insertion Loss with a TDT
E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler
E.3 Differential TDR/TDT Measurements
References
F S-Parameters
F.1 Simulating and Synthesizing Time-Domain Responses from S-Parameters
F.2 S-Parameters of Coupled Differential Pairs and Structures
References
G Engineering CAD Tools
G.1 Circuit Simulators
G.2 3D EM Field Solvers
G.3 2D Planar Field Solvers
G.4 Power Integrity
G.5 Model Generation
G.6 Other Tools
References
H Test Fixture Evaluation andCharacterization
H.1 Measuring the Test Fixture Performance
H.1.1 Test Coupons
H.1.2 Test Fixture Socket and Socket Via Field Probing
H.2 Measuring the Test Fixture Power Distribution Network
References
I Jitter Injection Calibration
I.1 Sinusoidal Jitter Injection Calibration
I.1.1 The J1=J0 Bessel Approach
I.1.2 The RJ Subtraction Approach
I.2 Random Jitter Injection Calibration
I.3 ISI Jitter Injection Calibration
References
About the Authors
Index

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Engineer's Guide to Automated Testing of High-Speed Interfaces

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