
Engineer's Guide to Automated Testing of High-Speed Interfaces, Second Edition
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Content
- Intro
- Contents
- Preface to the Second Edition
- Preface to the First Edition
- 1 Introduction
- 1.1 Characterization and Design Verification
- 1.2 Production Testing
- 1.3 Accuracy and Correlation
- 1.4 The ATE Test Fixture
- 1.5 The Future
- 2 High-Speed Digital Basics
- 2.1 High-Speed Digital Signaling
- 2.2 Time and Frequency-Domains
- 2.3 Bit Error Rate
- 2.4 Jitter
- 2.5 Classification of High-Speed I/O Interfaces
- 2.6 Hardware Building Blocks and Concepts
- 2.7 Multilevel Signaling
- 3 High-Speed Interface Standards
- 3.1 PCI Express
- 3.2 XDR DRAM
- 3.3 GDDR SDRAM
- 3.4 MIPI Standards
- 3.5 Other High-Speed Digital Interface Standards
- 4 ATE Instrumentation for Digital Applications
- 4.1 ATE Timing Architectures
- 4.2 Digital Pin Electronics ATE Card
- 4.3 Sampler/Digitizer ATE Card
- 4.4 Parametric Measurements with Sampled Data
- 4.5 Power Supplies
- 5 Tests and Measurements
- 5.1 Bit and Pattern Alignment
- 5.2 Functional Test
- 5.3 Shmoo Tests
- 5.4 Fundamental Driver Tests
- 5.5 Driver Jitter Tests
- 5.6 Fundamental Receiver Tests
- 5.7 Receiver Jitter Tolerance
- 5.8 PLL Characterization
- 5.9 Other Tests
- 5.10 Power Consumption During IC Testing
- 5.11 Measurement Errors
- 6 Production Testing
- 6.1 Golden Device
- 6.2 System-Level Test
- 6.3 Instrument-Based Testing: At-Speed ATE
- 6.4 Instrument-Based Testing: Low-Speed ATE
- 6.5 Instrument-Based Testing: Bench Instrumentation
- 6.6 Active Test Fixture
- 6.7 Multi-site Testing
- 7 Support Instrumentation
- 7.1 Oscilloscopes
- 7.2 Bit Error Rate Tester
- 7.3 Time Interval Analyzer
- 7.4 Time-Domain Reflectrometry/Transmission(TDR/TDT)
- 7.5 Spectrum Analyzer
- 7.6 Signal Source Analyzer
- 7.7 Vector Network Analyzer
- 7.8 Arbitrary Waveform and Function Generators
- 7.9 Noise Generators
- 7.10 Sinusoidal Clock Sources
- 7.11 Clock and Data Recovery
- 7.12 Protocol Analyzer
- 7.13 Switch Matrix
- 7.14 Isolation Transformer
- 7.15 Connecting Bench Instrumentation to an ATESystem
- 7.16 Coaxial Cables and Connectors
- 7.17 Accessories
- 8 Test Fixture Design
- 8.1 Test Fixtures
- 8.2 High-Speed Design Effects
- 8.3 Impedance Controlled Routing
- 8.4 Stack-Up
- 8.5 Via Transitions
- 8.6 Coaxial Connector Footprint Design
- 8.7 DUT BGA Ballout
- 8.8 Relays
- 8.9 Bidirectional Layout
- 8.10 Sockets
- 8.11 Power Distribution Network Design
- 8.12 HIFIX
- 8.13 Wafer Probing
- 9 Advanced ATE Topics
- 9.1 ATE Specifications and Calibration
- 9.2 Multiplexing of ATE Channels
- 9.3 Focus Calibration
- 9.4 Testing of High-Speed Bidirectional Interfaceswith a Dual Transmission Line Approach
- 9.5 Including the DUT Receiver Data Recovery inDriver Tests
- 9.6 DUT Reference Clock Jitter AttenuationApproaches
- 9.7 Protocol-Awareness and Protocol-Based Testing
- 9.8 Testing Multilevel Interfaces with Standard DigitalATE Pin Electronics
- 9.9 Signal Path Characterization and Compensation
- 9.10 Test Fixture and ATE Pin Electronics Co-Simulation
- 9.11 ATE DC Level Adjustments
- A Introduction to the Gaussian Distribution and Analytical Computation of the BER
- A.1 The Gaussian Distribution
- A.2 Computation of the BER for a System with OnlyGaussian Random Jitter
- A.3 Computation of the a(BER) Value
- A.4 Properties of the Error Function erf(x) andComplementary Error Function erfc(x)
- B The Dual Dirac Model and RJ/DJ Separation
- B.1 The Dual Dirac Jitter Model
- B.2 RJ/DJ Separation with the Q-Factor Algorithm
- C Pseudo-Random Bit Sequences and Other Data Patterns
- C.1 Pseudo-Random Bit Sequences
- C.2 Pseudo-Random Word Sequences
- C.3 Other Important Patterns
- D Coding, Scrambling, Disparity, and CRC
- D.1 Disparity
- D.2 8B/10B Coding
- D.3 128B/130B Coding
- D.4 Scrambling
- D.5 Error Detection
- E Time-Domain Reflectometry and Time-Domain Transmission (TDR/TDT)
- E.1 TDR
- E.2 TDT
- E.3 Differential TDR/TDT Measurements
- F S-Parameters
- F.1 Simulating and Synthesizing Time-DomainResponses from S-ParametersAs mentioned
- F.2 S-Parameters of Coupled Differential Pairs andStructures
- F.3 S-Parameters: Calibration and De-Embedding
- G Engineering CAD Tools
- G.1 Circuit Simulators
- G.2 3D EM Field Solvers
- G.3 2D Planar Field Solvers
- G.4 Power Integrity
- G.5 Model Generation
- G.6 Other Tools
- H Test Fixture Evaluation and Characterization
- H.1 Measuring the Test Fixture Signal Performance
- H.2 Measuring the Test Fixture Power DistributionNetwork
- I Jitter Injection Calibration
- I.1 Sinusoidal Jitter Injection Calibration
- I.2 Random Jitter Injection Calibration
- I.3 ISI Jitter Injection Calibration
- J Phase Noise, RMS Jitter, and Random Jitter
- About the Authors
- Index
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