FSM-based Digital Design using Verilog HDL
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Persons
Peter D. Minns, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Dr Peter Minns has been at Northumbria University since 1984, now holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences. He teaches courses on electrical circuit theory, electronics, programming and embedded system design to both undergraduates and post graduates, and is also involved in teaching company schemes in industry. Previous to this, he has worked for many years as a practising engineer specializing in both the telecommunications and embedded microprocessor fields. His current research interest is in the development of finite state machines (FSMs).
Ian David Elliott, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Ian Elliott has been a lecturer in further and higher education for over 20 years, currently holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences, at Northumbria University. He has taught a wide range of subjects in the field of electronics, as well as working as a consultant in industry, carrying out research into integrated circuit testing. He now specializes in hardware description languages, specifically Verilog-HDL and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). He was one of the first academics to introduce the topic of hardware description languages into the curriculum.
Content
Introduction
What is a Finite State Machine
Number of States
Number required for State Diagram - Frame 1.3
Mealy FSM
Moore FSM
Class C FSM
Introduction to the State Diagram - States, Transitions & Inputs
Input Signals - Frames 1.8 to 1.9,
Output Signals - Frame 1.9
Inputs and Outputs of FSM
Inverted Inputs - Frame 1.11
Active High Signals - Frames 1.11
Assignment - Frame 1.11
Non-Unit Distance Coding - Frame 1.11
Secondary State Variables
Unit Distance Coding - Frame 1.12 to Frame 1.14.
Active Low Signals - Frame 1.14
Mealy Outputs - Frame 1.16, 1.19, 1.20, 1.21, from
Effect of clock on Mealy output signals
Summary - Frame 1.22
CHAPTER 2 - CONTROLLING OUTSIDE WORLD DEVICES
Introduction
Using Timer to Introduce Wait States - Frame 2.1 to 2.3
Analogue to Digital Converters - Frame 2.4
Data Acquisition System - Frame 2.4, Frame 2.9 & Frame 2.10 from
Memory:
How to Control in FSM's - Frame 2.5 to 2.10
Chip Select & Read and Write Sequences
Frames 2.5 to 2.7 - (See also Chapter 4, Section 4.4,
Chapter 5, Sections 5.2, 5.3, 5.4, 5.6, 5.8.)
Monitoring Inputs for Changes - Frame 2.11 to 2.14
Dealing with Incorrect Input States - Frame 2.14
Summary
CHAPTER 3 - SYNTHESISING FSMS
Introduction
Synthesising using T Type Flip Flops - Frame 3.1 to 3.7
T Type Flip Flop
T Flip Flop Example in a State Diagram
Developing T Flip Flop Equations from the State Diagram
Examples of Developing T Equations from a Number of State Diagrams
Solutions to the Examples
D Type Flip Flops
Developing D Flip Flop Equations from a State Diagram
Rule 1: Dealing with 1 to 0 with Input Terms
Rule 2: Dealing with 1 to 1 Transitions
Rule 3: Dealing with two-way Branches
Using the Two-way Branch Rule
Examples of Obtaining D Flip Flop Equations from a State Diagram
State Diagram with Two-way Branch States: Obtaining D Type Equations
Resetting the Flip Flop
Examples of Developing D Equations from a Number of State Diagrams
Solutions to the Examples
Asynchronous and Synchronous Resetting of Flip Flops
Complete Design of Circuit for a Particular Design
Dealing with Multi-way Branch States using D Type Flip Flops
Dealing with Active Low Output Signals in an FSM
Dealing with Active Low Mealy Output Signals in an FSM
Summary
CHAPTER 4 - SYNCHRONOUS FSM DESIGNS
4.1 Traditional FSM Design Method Verses Method used in this Book
4.2 Dealing with Unused States
4.3 High/Low Alarm Indicator System
4.4 Simple Waveform Generator
4.5 Dice Game
4.6 Binary Data Serial Transmitter
4.7 Development of a Serial Asynchronous Receiver
4.8 Adding Parity Detection to the Serial Receiver System
4.9 Asynchronous Serial Transmitter System
4.10 Clocked Watchdog Timer
4.11 Summary
CHAPTER 5 -ONE HOT DESIGNS
5.1 One Hot Technique of FSM Design
5.2 Data Acquisition System (DAS)
5.3 A Shared Memory System
5.4 Fast Waveform Synthesiser
5.5 Controlling the FSM from a Microprocessor
5.6 Memory Chip Tester
5.7 Comparing One Hot Solution with more Conventional Design
Method of Chapter 4
5.8 Dynamic Memory Access (DMA) Controller
5.9 How to Control the DMA Controller from a Microprocessor
5.10 Detecting Binary Sequences using an FSM
5.11 Summary
CHAPTER 6 - INTRODUCTION TO VERILOG-HDL
- A Brief Background to HDLs
- Hardware Modelling with Verilog-HDL - the Module
- Modules within Modules : Creating Hierarchy
- Verilog-HDL Simulation : A Complete Example
- References and Further Reading
CHAPTER 7 - ELEMENTS OF VERILOG-HDL
- Built-in Primitives and Types
7.1.1 Verilog Types
7.1.2 Verilog Logic and Numeric Values
7.1.3 Specifying Values
7.1.4 Verilog-HDL Primitive Gates - Operators and Expressions
- Example Illustrating the use of Verilog-HDL Operators -
Hamming Code Encoder - References and Further Reading
CHAPTER 8 - DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG=HDL
- The Data Flow Style of Description - Review of the
Continuous Assignment - The Behavioural Style of Description - The Sequential Block
- Assignments within Sequential Blocks : Blocking and
Non-Blocking - Describing Combinational Logic using a Sequential Block
- Describing Sequential Logic using a Sequential Block
- Describing Memories
- Describing Finite State Machines:
Example 1 Chess Clock Controller FSM
Example 2 Combinational Lock FSM with Automatic
Lock Feature - References and Further Reading
CHAPTER 9 - ASYNCHRONOUS FSM DESIGN
9.1 Introduction
9.2 Development of Event Driven Logic
9.3 Using the Sequential Equations to Synthesise an Event FSM
9.3.1 Short Cut Rule
9.4 Implementing the Design using Sum of Product as PLD
9.5 Development of an Event Version of the Single Pulse Generator
with Memory FSM
9.6 Another event FSM design through to simulation
9.7 The Hover Mower FSM
9.8 An Example with a Transition Without any Input
9.9 Unusual Example responding to a Microprocessor
Address Location
9.10 Example that uses a Mealy Output
9.11 Example using a Relay Circuit
9.12 Race Conditions in Event FSMs
9.13 Wait State Generator for a Microprocessor System
9.14 Development of an Asynchronous FSM to Control a Clothes
Spin System
9.15 Summary
CHAPTER 10 - PETRI-NETS
10.1 Introduction to Simple Petri-Nets
10.2 Sequential Petri-Net Example, the Pump Spin Motor Problem
10.3 Parallel Petri-Nets
10.4 Synchronising Flow in a Parallel Petri-Net
10.5 Using Enabling/Disabling Arcs to Synchronise Flow between
Two Petri-Nets
10.6 Example - Control of Shared Resource
10.7 A Serial Receiver of Binary Data using a Petri-Net Controller
10.8 Summary
APPENDIX INDEX
APPENDIX A1 - LOGIC GATES AND BOOLEAN ALGEBRA IN THE BOOK
Introduction
A1.1 Basic Gate Symbols used in the Book
A1.2 Exclusive OR and Exclusive NOR Symbols
A1.3 Laws of Boolean Algebra:
A1.3.1 Basic OR Rules
A1.3.2 Basic AND Rules
A1.3.3 Associative Laws and Commutative Laws
A1.3.4 Distributive Laws
A1.3.5 Auxiliary Law - For Static 1 Hazard Removal
A1.3.5.1 Proof of the Auxiliary Law
A1.3.6 The Consensus Theorem
A1.3.7 Effect of Signal Delay on Logic Gates
A1.3.8 De-Morgans Theorem
A1.4 Examples of Applying the Laws of Boolean Algebra
A1.4.1 Converting AND-OR to NAND
A1.4.2 Converting AND-OR to NOR
A1.4.3 Logical Adjacency Rule
A1.5 Summary
APPENDIX A2 - COUNTING & SHIFTING CIRCUIT TECHNIQUES
Introduction
A2.1 Basic Up Down Synchronous Binary Counter Development
A2.2 Example of a Four Bit Synchronous up Counter using T Flip Flops
A2.3 Parallel Loading Counters
A2.4 Using D Flip Flops to Build Parallel Loading Counters
A2.5 Simple Binary Up Counter
A2.6 Clock Circuit to Drive the Counter (and FSMs)
A2.7 Counter Design using Don't Cares
A2.8 Shift Registers
A2.9 Asynchronous Receiver Details for Section 4.7 Chapter 4
A2.9.1 Eleven Bit Shift Register for the Asynchronous
Receiver Module
A2.9.2 Divide by Eleven Counter
A2.9.3 Complete Simulation of the Asynchronous
Receiver System
A2.10 Summary
APPENDIX A3 - TUTORIAL ON THE USE OF VERILOG HDL
TO SIMULATE AN FSM DESIGN
A3.1 Introduction
A3.2 Single Pulse with Memory Synchronous FSM Design
A3.2.1 Specification
A3.2.2 Block Diagram
A3.2.3 State Diagram
A3.2.4 Equations from the State Diagram
A3.2.5 Translation into a Verilog Description
A3.3 Test Bench Module and its Purpose
A3.4 Using the Verilogger Simulator
A3.4.1 Output from the Simulator
A3.5 Summary
APPENDIX A4 - IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURAL MODE
A4.1 Introduction
A4.2 Example 1- The Single Pulse with Memory FSM Revisited
A4.3 The Memory Tester in Chapter 5, Section 5.6 Revisited
A4.4 Summary
