Digital Signal Processing with Field Programmable Gate Arrays
Description
- Over 10 new system level case studies designed in VHDL and Verilog
- A new chapter on image and video processing
- An Altera Quartus update and new Model Sim simulations
- Xilinx Atlys board and ISIM simulation support
- Signed fixed point and floating point IEEE library examples
- An overview on parallel all-pass IIR filter design
- ICA and PCA system level designs
- Speech and audio coding for MP3 and ADPCM
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Dr. Uwe Meyer-Baese received his BSEE, MSEE, and Ph.D. "Summa cum Laude" from the Darmstadt University of Technology in 1987, 1989 and 1995, respectively. He is now an Full Professor in the ECE Department at Florida State University. He holds 3 patents, has published over 100 journal and conference papers, 6 books and supervised more than 60 master and Ph.D. thesis projects in the real-time DSP/FPGA area. In 2003, he was awarded the "Habilitation" (venia legendi) by the Darmstadt University of Technology. He is PI and CO-PI of projects valued more than 9 million USD. His research is funded by NIH, NSF, FSU, DOD, Harris, SUN microsystems, Altera, Xilinx and the State of Florida. He is author of the best-selling textbook on DSP with FPGAs by Springer Verlag sold over 20K copies. He received in 1997 the Max-Kade Award in Neuroengineering, the Outstanding Teaching Award from Florida State University in 2008, the Best Presentation Award from SPIE in 2006, Who's Who in Science member in 2005, and the Humboldt Research Award in 2009. Dr. Meyer-Baese has been promoted by the Institute of Electrical and Electronics Engineers (IEEE) to Senior Member status in 2013.
