Source-Synchronous Networks-On-Chip
Circuit and Architectural Interconnect Modeling
1st Edition
Published on 19. November 2013
XIII, 143 pages
978-1-4614-9405-8 (ISBN)
Description
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
More details
Series
Language
English
Place of publication
New York
United States
Publishing group
Springer US
Target group
Professional and scholarly
Product notice
Reflowable
Illustrations
XIII, 143 p. 95 illus., 10 illus. in color.
File size
6,61 MB
ISBN-13
978-1-4614-9405-8 (9781461494058)
DOI
10.1007/978-1-4614-9405-8
Schweitzer Classification
Other editions
Additional editions
Ayan Mandal | Sunil P. Khatri | Rabi Mahapatra
Source-Synchronous Networks-On-Chip
Circuit and Architectural Interconnect Modeling
Book
11/2013
Springer
€106.99
Shipment within 15-20 days
Content
Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.
