Networks-on-Chip
From Implementations to Programming Paradigms
Published on 4. December 2014
382 pages
978-0-12-801178-2 (ISBN)
Description
Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.
This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.
- Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
- The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
- Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
- Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.
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Other editions
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Book
12/2014
Morgan Kaufmann
€60.50
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Persons
Sheng Ma received the B.S. and Ph.D. degrees in computer science and technology from the National University of Defense Technology (NUDT) in 2007 and 2012, respectively. He visited the University of Toronto from Sept. 2010 to Sept. 2012. He is currently an Assistant Professor of the College of Computer, NUDT. His research interests include on-chip networks, SIMD architectures and arithmetic unit designs.Libo Huang received the B.S. and Ph.D. degree in computer engineering from National University of Defense Technology, PR China, in 2005 and 2010 respectively. From 2010, he was a Lecturer with the Department of Computer Science. His research interests include computer architecture, hardware/software Codesign, VLSI design, on-chip communication. He served as the technical reviewer of several conference and journals, e.g. MEJ, IJHPSA, ICCE 2010. Since 2004, he authored more than 20 papers in internationally recognized journals and conferencesMingche Lai received the PhD degree in computer engineering from NUDT in 2008. Currently, he is an Associate Professor with College of Computer, NUDT, and employed to develop high-performance computer interconnection systems. Since 2008, he has also been a Faculty Member with National Key Laboratory for Parallel and Distributed Processing of China. His research interests include on-chip networks, optical communication, many-core processor architecture, hardware/software co-design. He is a member of the IEEE and ACMWei Shi received the PhD degree in computer Science from the National University of Defense Technology (NUDT) in 2010. Currently, he is an Assistant Professor of the College of Computer, NUDT, and employed to develop high-performance processors. His research interests include computer architecture, VLSI design, on-chip communication and asynchronous circuit techniques
Content
1 Introduction
Part One: Logic Implementations
2 A Single-cycle Router with Wing Channel
3 Dynamic VC Routers with Congestion Awareness
4 A NoC Topology with Virtual Bus
Part Two: Routing and Flow Control
5 Routing Algorithms for Workload Consolidation
6 Flow Control for Fully Adaptive Routing
7 Deadlock-free Flow Control for Torus NoCs
8 Delay Analysis based on the M/G/1/N Queuing Model
Part Three: Programming Paradigms
9 Support Cache-coherent Collective Communication
10 Optimizations to Exploit Communication Locality
11 Customizations for MPI Primitives
12 Conclusions and Future Work
