Design of Semiconductor QCA Systems
1st Edition
Published on 1. January 2013
256 pages
978-1-60807-688-8 (ISBN)
Description
Integrated circuits have become smaller, cheaper, and more reliable and certainly have revolutionized the world of electronics. Integrated circuits are used in almost all electronic devices and systems, many of which, such as the Internet, computers, and mobile phones, have become essential parts of modern life and have changed the way we live. Quantum-dot cellular automata (QCA) provides a revolutionary approach to computing with device-to-device interactions. The design of a QCA circuit is radically different from a conventional digital design due to its unique characteristics at both the physical level and logic level. Research on both circuit architecture and device design is required for a profound understanding of QCA nanotechnologies. This detailed reference presents practical design aspects of QCA with an emphasis on developing real-world implementations.
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Additional editions
Weiqiang Liu | Maire O'Neill | Earl Swartzlander
Design of Semiconductor QCA Systems
Book
10/2013
Artech House Publishers
€203.52
Shipment within 10-20 days
Content
- Intro
- Design of Semiconductor QCA Systems
- Contents
- Part I QCA Background
- 1 Introduction
- 1.1 Motivation
- 1.2 Contributions
- 1.3 Book Outline
- References
- 2 Quantum-dot Cellular Automata
- 2.1 QCA Fundamentals
- 2.1.1 QCA Cells and Wires
- 2.1.2 QCA Basic Gates
- 2.1.3 QCA Wire Crossings
- 2.2 Physical Implementations of QCA
- 2.2.1 Metal-Island QCA
- 2.2.2 Semiconductor QCA
- 2.2.3 Molecular QCA
- 2.2.4 Magnetic QCA
- 2.3 Clocking Schemes
- 2.3.1 Typical Four-Phase Clocking
- 2.3.2 Clocking Floorplans
- 2.3.3 Clocking for Reversible Computing
- 2.4 Design and Simulation Tools
- 2.4.1 QCADesigner
- 2.4.2 QCAPro
- 2.5 Research Into QCA Digital Design
- 2.5.1 Computer Arithmetic Circuits
- 2.5.2 Combinational Circuits
- 2.5.3 Latches and Sequential Circuits
- 2.5.4 Memory Design
- 2.5.5 General and Specific Processors
- 2.5.6 Design Methods and Design Automation
- 2.5.7 Testing, Defects and Faults
- 2.6 Basic Design Rules
- 2.6.1 Layout Rules
- 2.6.2 Timing Rules
- 2.7 Summary
- References
- Part II QCA Arithmetic Circuits
- 3 QCA Adders
- 3.1 Introduction
- 3.2 Ripple Carry Adder
- 3.2.1 Architectural Design
- 3.2.2 Schematic Design
- 3.2.3 Layout Design
- 3.3 Carry Lookahead Adder
- 3.3.1 Architectural Design
- 3.3.2 Schematic Design
- 3.3.3 Layout Design
- 3.3.4 Simulation Results
- 3.4 Conditional Sum Adder
- 3.4.1 Architectural Design
- 3.4.2 Schematic Design
- 3.4.3 Layout Design
- 3.5 Comparison of the Conventional Adders
- 3.6 Carry Flow Adder
- 3.6.1 Basic Design Approach
- 3.6.2 Carry Flow Full Adder Design
- 3.6.3 Simulation Results
- 3.7 Decimal Adder
- 3.7.1 Conventional BCD Adder
- 3.7.2 Carry Lookahead Decimal Adder
- 3.7.3 Comparison and Analysis
- 3.8 Conclusion
- References
- 4 QCA Multipliers
- 4.1 Introduction
- 4.2 QCA Array Multipliers
- 4.2.1 Structural Design
- 4.2.2 Schematic Design
- 4.2.3 Implementation of Array Multipliers With QCAs
- 4.3 Wallace and Dadda Multipliers For QCA
- 4.3.1 Introduction
- 4.3.2 Schematic Design
- 4.3.3 Implementation of Wallace and Dadda Multipliers With QCAs
- 4.4 Quasi-Modular Multipliers For QCA
- 4.4.1 Quasi-Modular Multiplier Method
- 4.4.2 Structural Design
- 4.4.3 Implementation of Quasi-Modular Multipliers With QCAs
- 4.4.4 Simulation Results
- 4.5 Comparison of QCA Multipliers
- 4.6 Conclusion
- References
- 5 QCA Dividers
- 5.1 Introduction
- 5.2 Digit Recurrent Divider
- 5.2.1 Types of Digit Recurrent Dividers
- 5.2.2 Conventional Restoring Binary Divider Architecture
- 5.2.3 Restoring Binary Divider
- 5.2.4 Implementation of the Restoring Divider
- 5.2.5 Simulation Results
- 5.3 Convergent Divider
- 5.3.1 The Goldschmidt Division Algorithm
- 5.3.2 The Data Tag Method for Iterative Computation
- 5.3.3 Implementation of the Goldschmidt Divider
- 5.3.4 Simulation Results
- 5.4 Conclusion
- References
- Part III QCA Design Methodologies
- 6 Design of QCA Circuits Using Cut-Set Retiming
- 6.1 Introduction
- 6.2 QCA Timing Constraints and Timing Issues
- 6.2.1 Timing Constraint I
- 6.2.2 Timing Constraint II
- 6.2.3 Timing Issues in QCA
- 6.3 Data Flow Graph and Retiming Technique
- 6.3.1 Data Flow Graph
- 6.3.2 Mapping CMOS DFG to QCA DFG
- 6.3.3 Retiming Technique
- 6.4 A Cut-Set Retiming Design Procedure
- 6.4.1 Cut-Set Retiming and Its Rules
- 6.4.2 Proposed Cut-Set Retiming Design Procedure
- 6.5 Case Studies
- 6.5.1 MMM Design
- 6.5.2 S27 Benchmark Circuit Design
- 6.6 Conclusion
- References
- 7 QCA Systolic Array Design1
- 7.1 Introduction
- 7.2 Signal Flow Graph and Systolic Array Architecture
- 7.2.1 Signal Flow Graph
- 7.2.2 Systolic Array Architecture
- 7.3 Case Study I: Matrix Multiplier
- 7.3.1 Systolic Array Matrix Multiplier Introduction
- 7.3.2 QCA Systolic Matrix Multiplier Design
- 7.3.3 Design Study
- 7.4 Case Study II: Galois Field Multiplier
- 7.4.1 Galois Field Multiplier Introduction
- 7.4.2 QCA Systolic Galois Field Multiplier Design
- 7.4.3 QCA Single Processor Galois Field Multiplier Design
- 7.4.4 Design Study
- 7.5 QCA Systolic Array Design Methodology
- 7.6 Conclusion
- References
- 8 Evaluation of QCA Circuits with New Cost Functions
- 8.1 Introduction
- 8.2 QCA Cost Metrics and Cost Functions
- 8.2.1 Area/Complexity
- 8.2.2 Delay
- 8.2.3 Irreversible Power Dissipation
- 8.2.4 Number of Crossovers
- 8.2.5 Proposed QCA Cost Functions
- 8.3 Overview of QCA Adders
- 8.3.1 Coplanar Adders
- 8.3.2 Multilayer Adders
- 8.4 Comparison of QCA Adders With Proposed Cost Functions
- 8.4.1 Comparison with Individual Metrics
- 8.4.2 Comparison with QCA Cost Function I
- 8.4.3 Comparison with QCA Cost Function II
- 8.4.4 Discussion
- 8.5 Conclusion
- References
- 9 Conclusion and Future Work
- 9.1 Conclusion
- 9.2 Future Work
- 9.2.1 QCA Design Automation Tools
- 9.2.2 Finite State Machine Design
- 9.2.3 Reversible Circuit Design
- 9.2.4 Decimal Arithmetic
- References
- About the Authors
- Index
