Dual Mode Logic
Description
This book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic.
- Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size);
- Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance;
- Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells;
- Illustrates DML efficiency for a variety of VLSI applications.
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Persons
Itamar Levi earned his B.Sc. and M.Sc. degrees in Electrical and Computer Engineering as a part of a direct excellence student track from Ben-Gurion University in 2012 and 2013, respectively. He completed his Ph.D. at Bar-Ilan University in 2017. He was a research-associate in UCLouvain, Belgium until 2019 with the UCLouvains Crypto-Group and currently he is a Computer-Engineering Faculty member at Bar-Ilan University, in Ramat Gan, Israel. He is also a member of Emerging Nanoscale Circuits and Systems Labs (EnICS), at BIU. Dr. Levi's research interest include digital circuit design, embedded systems security, security evaluation analysis for cryptographic devices, side-channel and fault-injection countermeasures and cryptographic implementations.
Dr. Levi has served in the Technical Program Committee of IEEE HOST, MAL-IoT conferences ASHES workshop and has been an active reviewer of IEEE TCAS-1 and TCAS-2, IEEE TVLSI, IEEE ACCESS, Elsevier MEJ, Elsevier Integration, The VLSI Journal, IEEE sensors, MDPI JLPEA and MDPI Electronics and MDPI Cryptography journals as well as IEEE ISCAS, IEEE ICECS, IEEE Sensors, IEEE HOST, ASHES, and MAL-IoT conferences. He has published over 40 journal and conference papers, gave numerous invited talks and has submitted 10 patents applications, 7 of which already granted.
Alexander Fish received his B.Sc. degree in Electrical Engineering from the Technion, Israel Institute of Technology, Haifa, Israel, in 1999. He completed his M.Sc. in 2002 and his Ph.D. (summa cum laude) in 2006, respectively, at Ben-Gurion University in Israel. He was a postdoctoral fellow in the ATIPS laboratory at the University of Calgary (Canada) from 2006-2008. In 2008 he joined Ben-Gurion University in Israel, as a faculty member in the Electrical and Computer Engineering Department. There he founded the Low Power Circuits and Systems (LPC&S) laboratory, specializing in low power circuits and systems. In October 2012 Prof. Fish joined the Bar-Ilan University Faculty of Engineering as Associate Professor and the Head of the nanoelectronics track. In March 2015 he founded the Emerging Nanoscaled Integrated Circuits and Systems (ENICS) labs. Currently, he is Full Professor and heads the EnICS Impact Center.
Prof. Fish's research interests include power reduction methodologies for high speed digital and mixed signal VLSI chips, energy efficient SRAM and eDRAM memory arrays, CMOS image sensors and biomedical circuits, systems and applications and hardware security. He has authored over 180 scientific papers in journals and conferences. He has also submitted more than 30 patent applications of which 14 have been granted. Prof. Fish has published three book chapters and two books as an editor.Prof. Fish founded and served as Editor in Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) from 2012 to 2018. He is Associate Editor ofthe IEEE Sensors Journal, IEEE Access Journal, Microelectronics Journal (Elsevier) and Integration, and the VLSI journal (Elsiever). He has also served as the chair of different tracks of various IEEE conferences.
Content
Chapter 1. Introduction.- Chapter 2. Introduction to Dual Mode Logic (DML).- Chapter 3. Optimization of DML Gates.- Chapter 4. Low Voltage DML.- Chapter 5. DML Energy-Delay Tradeoffs and Optimization.- Chapter 6. DML Control.- Chapter 7. Towards a DML Library Characterization and Design with Standard Flow.- Chapter 8. Towards a DML Optimized Synthesis.- Chapter 9. Dual Mode Logic in FD-SOI Technology. Chapter 10. Conclusion.
