Code Optimization Techniques for Embedded Processors
Methods, Algorithms, and Tools
Published on 9. March 2013
VIII, 216 pages
978-1-4757-3169-9 (ISBN)
Description
The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Traditionally, these embedded processors mostly have been pro grammed in assembly languages due to efficiency reasons. This implies time consuming programming, extensive debugging, and low code portability. The requirements of short time-to-market and dependability of embedded systems are obviously much better met by using high-level language (e.g. C) compil ers instead of assembly. However, the use of C compilers frequently incurs a code quality overhead as compared to manually written assembly programs. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice. In turn, this requires new compiler techniques that take the specific constraints in embedded system de sign into account. An example are the specialized architectures of recent DSP and multimedia processors, which are not yet sufficiently exploited by existing compilers.
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Content
1. Introduction.- 2. Memory Address Computation for DSPS.- 3. Register Allocation for DSP Data Paths.- 4. Instruction Scheduling for Clustered VLIW Processors.- 5. Code Selection for Multimedia Processors.- 6. Performance Optimization with Conditional Instructions.- 7. Function Inlining under Code Size Constraints.- 8. Frontend Issues - The Lance System.- 9. Conclusions.- Appendices.- A- Experimental Result Tables.- B- Example for the LANCE V2.0 IR.- References.- About the Author.
