
Spin Transfer Torque (STT) Based Devices, Circuits, and Memory
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Content
- Intro
- Spin Transfer Torque Based Devices, Circuits, and Memory
- Contents
- Preface
- 1 Introduction to Magnetic Memories and STT
- 1.1 Electron Spin and FM Materials: Some Basic Concepts
- 1.1.1 Magnetic Moment of a Single Electron
- 1.1.2 Magnetization, Spin Polarization, and Spin Filtering
- 1.1.3 Electrical Spin Injection
- 1.2 Spin Valve and GMR Effect
- 1.3 Vector Spin Polarization
- 1.4 Theory of Magnetization Dynamics
- 1.4.1 Gyromagnetic Precession
- 1.4.2 Damping
- 1.4.3 Landau-Lifschitz-Gibert Equation
- 1.5 STT and LLGS Equation
- 1.5.1 Direction of STT
- 1.5.2 Magnitude of STT
- 1.5.3 STT in Magnetic Multilayers and Spin Torque Efficiency
- 1.5.4 Overview of Internal fields
- Summary
- References
- 2 MTJs
- 2.1 Thin Film Magnetism: In-Plane and Perpendicular Magnetic Anisotropy
- 2.2 MTJ Architecture and Operation
- 2.2.1 Precessional Switching (PS)
- 2.2.2 Thermally Assisted Switching (TAS){AU: previously the acronym TSA was "temperature-assisted switching." Pls make consistent or alter the use of the acronym as necessary.}
- 2.3 Recent Experimental Data and PMA MTJ Scaling
- 2.4 MTJ Conductance and TMR
- 2.5 Simulation Program with Integrated Circuit Emphasis (SPICE) Modeling of MTJs
- 2.6 Micromagnetic Modeling of MTJs
- 2.6.1 Implementation of the STT Term
- 2.6.2 Implementation of Energy Terms
- 2.6.3 Micromagnetic Simulation of Magnetization Dynamics
- 2.7 Novel Architectures and Electric Field-Assisted Switching
- 2.7.1 Giant Spin Hall Effect based MTJs
- 2.7.2 Electric Field-Assisted Switching
- 2.8 MTJ-Based Stateful Logic Gates
- 2.9 MTJs Exploiting TAS
- Summary
- References
- 3 STT MRAMs
- 3.1 Cell and Array Architectures
- 3.2 Operation of STT MRAMs
- 3.2.1 Read and Write Mechanism
- 3.2.2 I-V and R-V Characteristics of a STT MRAM Cell
- 3.2.3 Load line Analysis
- 3.3 STT MRAM Performance Parameters
- 3.4 STT MRAM Cell Layout
- 3.5 STT MRAM Design and Simulation
- 3.5.1 Simulation Methodology
- 3.5.2 STT MRAM Design: A Case Study
- 3.5.3 Analysis of Standard-Connected and Reverse-Connected Cells
- 3.5.4 Comparison in Terms of Power, Area, and Speed
- 3.6 Fabrication of STT MRAMs
- 3.6.1 BEOL MTJ Processing
- 3.6.2 MTJ Processing: Deposition, Annealing, and Etching
- 3.6.3 Challenges in MTJ Fabrication
- 3.7 Novel STT MRAM
- 3.7.1 2T-1R STT MRAM Cell
- 3.7.2 GSHE-Based STT MRAMs
- 3.7.3 Multilevel Cell Design
- 3.8 Comparison with Other Memory Technologies
- Summary
- References
- 4 Hybrid MTJ-CMOS Digital Circuits
- 4.1 Nonvolatile Combinational Circuits
- 4.2 Hybrid MTJ-CMOS-Based Reconfigurable Logic Gates
- 4.2.1 Hybrid CMOS/MTJ-Based Reconfigurable AND Operation
- 4.2.2 Hybrid CMOS/MTJ-Based Reconfigurable OR Operation
- 4.3 Hybrid MTJ-CMOS-Based FA
- 4.4 Nonvolatile Flip-Flop
- Summary
- References
- 5 Nonvolatile Computing with STT MRAMs
- 5.1 Nonvolatile and Normally OFF Computing Architectures
- 5.2 Hybrid Cache Memories
- 5.2.1 Nonvolatile DRAM-MRAM Cache
- 5.2.2 Nonvolatile SRAM-MRAM Cache
- 5.3 Low-Power Techniques for the STT MRAM Cache
- 5.3.1 EWT
- 5.3.2 WL Voltage Reduction
- 5.3.3 BL Clamping Technique
- 5.3.4 Asymmetric Access Devices
- 5.4 STT MRAM as a Main Memory
- Summary
- References
- 6 STT-Based All Spin Logic (ASL)
- 6.1 NLSV Devices
- 6.2 All Spin Logic (ASL)
- 6.3 Static and Clocked ASL
- 6.4 Modeling of NLSV and ASLD
- 6.4.1 Modeling the Spin Transport
- 6.4.2 Modeling of Magnetization Dynamics
- Summary
- References
- 7 Nonvolatile Computing with All Spin Information Processing
- 7.1 Implementation of Minimum Boolean Functions
- 7.1.1 Implementation of the NAND Operation
- 7.1.2 Implementation of NOR Operation
- 7.1.3 Implementation of AND and OR Operation
- 7.1.4 ASL Cascading
- 7.2 ASL-Based Latch and Flip-flop
- 7.2.1 ASL Latch
- 7.2.2 Flip-Flop
- 7.4 FAs
- 7.5 Nonvolatile Computing Architecture with ASL
- 7.6 Comparison and Challenges
- Summary
- References
- Appendix A SI-to-CGS Conversion of Basic Units Used in Magnetism
- Appendix B OOMMF .MIF Input file for Multilayer Micromagnetic Simulation of MTJ at 300K
- Appendix C HSPICE Net-list for STT MRAM Simulation: Case Study
- Appendix D HSPICE Net-list for Asymmetric STT MRAM Simulation
- Appendix E MATLAB Code for Simulation of Nonlocal Spin Valve Device
- Appendix F OOMMF Code for Micromagnetic Simulation of ASLD
- Appendix G MATLAB Code for Simulation of NAND and NOR ASL Gates
- About the Authors
- Index
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