Unleash the System On Chip using FPGAs and Handel C
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Chapter 1: Introduction. 1.1 Prologue. 1.2 Exceptional Attributes of the SoC Technology. 1.3 Classical taxonomy: a holistic perspective extended towards Integrated Circuits Classification. 1.4 System on Chip (SoC) Term and Scope. 1.5 Constituents of SoC. 1.6 Sprawling Growth of SoC market. 1.7 Choosing the platform, ASIC Vs FPGAs. 1.8 FPGA based Programmable SoC. 1.9 Orientation of the Book.
Chapter 2: Familiarizing with Handel C. 2.1 EDA Tools i.e. Computer Aids for VLSI Design. 2.2 Background of Hardware Description Languages. 2.3 Expressing abstraction at higher levels. 2.4 Where C stands amidst the well established HDLs? 2.5 Introducing Handel C. 2.6 Top Down or Bottom up? 2.7 Handel C: A boon for Software Professionals. 2.8 Handel C Vs ANSI C. 2.9 Handel C Design Flow.
Chapter 3: Sequential logic Design. 3.1 Design Philosophy of Sequential Logic. 3.2 D flip-flop. 3.3 Latch. 3.4 Realization of JK Flip-Flop. 3.5 Cell of Hex counter for Counter Applications. 3.6 Realization of Shift Register for SoC. 3.7 LFSR Core for Security Applications in SoC. 3.8 Clock Scaling and Delay Generation in SoC. 3.9 SoC Data Queuing using FIFO. 3.10 Implementation of Stack though LIFO. 3.11 Soft IP core for Hamming Code.
Chapter 4: Combinational Logic Design. 4.1 Introduction. 4.2 Design Metrics for the Combinational Logic Circuits: SoC Perspective. 4.3 Core of "2 to 4 decoder". 4.4 "3 to 8 decoder" using hierarchical approach. 4.5 Priority Encoder 4 to 2. 4.6 Soft IP Core of "7 to 3 encoder" Implementation. 4.7 IP core of 'Parity generator' for Communication Applications. 4.8 IP Core for Parity checker and error detection for Internet Protocol. 4.9 BCD TO Seven Segment converter. 4.10 Core of Binary to Gray Converter and Applications. 4.11 Realization of IP Core of Gray to Binary Converter. 4.12 Designing Barrel Shifters and their applications.
Chapter 5: Arithmetic core design and Design Reuseof Soft IP Cores. 5.1 Design Reuse Philosophy. 5.2 Advantages of on chip arithmetic. 5.3 Designing Half adder in Handel C. 5.4 Designing Full Adder as a Reusable Core. 5.5 Ripple Carry Adder on Chip. 5.6 Realization of Booth Algorithm using FPGA. 5.7 Building 8 bit ALU. 5.7 Third Party Tool Interface with Handel C. 5.8 Xilinx EDK Interface with Cores developed through Handel C.
Chapter 6: Rapid Prototyping of the Soft IP cores on FPGA. 6.1 Prototyping Philosophy. 6.2 Design and Prototyping of a Fuzzy Controller. 6.3 TCP/IP Packet Splitter Implementation Using Mixed Design Flow. 6.4. Linear Congruential Random Number Generator. 6.5 Implementation of Reusable Soft IP core of Blowfish Cipher.
Chapter 7: Soft Processor Core for Accelerated Embedded Design. 7.1 Building SoC for temperature control application using Picoblaze. 7.2 Hardware Software Codesign of SoC with built in Position Algorithm.
References. Index of Tables. Index of Figures. Index of Programs.
