Mainframe Computer Systems

Name: Mainframe Computer Systems | The General Electric Corporation
Brand: Cambridge Scholars Publishing
Price: 226.99 EUR
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The General Electric Corporation

Stephen H. Kaisler(Author)

Cambridge Scholars Publishing

1st Edition

Published on 22. October 2020

454 pages

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System requirements

978-1-5275-6116-8 (ISBN)

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Content

Intro
Table of Contents
Acknowledgement
List of Figures
List of Tables
General Electric Co. Computers
Chapter One
1.1 The ERMA Project
1.1.1 In the Beginning
1.1.2 The Contract
1.1.3 Selecting the Vendor
1.1.4 Operation
1.2 GE-100 System Architecture
1.3 GE-100 Peripherals
1.4 GE-115
Chapter Two
2.1 GE-205 and GE-210
2.1.1 GE-205 Computer System
2.1.2 GE-210 Computer System
2.2 GE-225
2.2.1 GE-225 System Configuration
2.2.2 Central Processing Unit
2.2.1.1 GE-225 Control Console
2.2.1.2 Registers
2.2.1.3 Instruction Execution
2.2.3 Main Memory
2.2.4 Auxiliary Arithmetic Unit
2.2.4.1 Operating Modes
2.2.4.2 AAU Registers
2.2.5 Concurrent Operation
2.2.6 Instruction Set
2.2.7 Interrupts
2.2.7.1 Priority Interrupts
2.2.7.2 Automatic Program Interrupt
2.2.8 GE 215
2.3 GE-225 System Peripherals
2.3.1 Paper Tape Reader-Punch
2.3.2 Card Reader and Card Punch
2.3.3 Controller Selector
2.3.4 Magnetic Tape Subsystem
2.3.4.1 Magnetic Tape Controller
2.3.4.2 MTC Registers
2.3.4.3 Magnetic Tape Handler
2.4.4.4. Checking Features
2.4.4.5 Magnetic Tape Characteristics
2.4.4.6 Programming Magnetic Tape Operations
2.4.4.7 Tape Movement Instructions
2.4.4.8 Tape Interrogation Instructions
2.3.5 High Speed Printer
2.3.6 Disc Storage Unit
2.3.7 Document Sorter
2.3.8 DATANET-15
2.3.9 Manual Peripheral Switch Control Unit
2.4 GE-225 System Software
2.4.1 GECOM
2.4.2 COBOL
2.4.3 ALGOL
2.4.4 TABSOL
2.4.4.1 Decision Table Basics
2.4.4.2 TABSOL Decision Table Preprocessor
2.4.4.3 TABSOL Assessment
2.4.5 Report Writer
2.4.6 FORTRAN II/IV
2.4.7 WIZOR
2.4.8 General Assembly Program
2.4.9 Subroutine Libraries
2.4.10 BRIDGE II
2.5 GE-235
2.5.1 GE-235 Central Processor
2.5.2 Storage Section
2.5.3 Arithmetic Section
2.5.4 Control Section
2.5.5 Auxiliary Arithmetic Unit
2.5.5.1 Operating Modes
2.5.5.2 AAU Registers
2.5.6 AAU Instruction Set
2.5.6.1 General Instructions
2.5.6.2 Arithmetic Operations
2.5.6.3 Test and Branch Instructions
2.6 Selector Channels
2.7 GE-235 Instruction Set
2.7.1 Arithmetic Instructions
2.7.2 Memory Transfers
2.7.3 Shift Instructions
2.7.4 Branch Instructions
2.7.5 Register Modification
2.8 GE-235 Peripherals
2.8.1 Punched Card Equipment
2.8.2 Magnetic Tape Subsystem
2.8.2.1 MTC Error Checking
2.8.2.2 MTC Registers
2.8.2.3 Control Switches
2.8.2.4 Magnetic Tape Handler
2.8.2.5 Magnetic Tape
2.8.3 Disc Storage Unit
2.8.4 Peripheral Switch Console
2.9 DATANET Communications Processors
2.10 GE-250
2.11 GE-265 Time-sharing System
2.11.1 Communications Hardware
2.11.2 Remote Terminals
Chapter Three
3.1 DN-30 System Architecture
3.1.1 Central Processor
3.1.2 Main Memory
3.1.3 Buffer Selector
3.1.4 Bit Buffer Unit Module
3.1.5 Character/Word Buffer Unit
3.1.6 Computer Interface Unit
3.1.7 Page Control Logic Unit
3.1.8 System Bus
3.1.9 I/O Multiplexor
3.2 I/O Channels
3.3 DN-30 Operation
3.4 DN-30 Instruction Set
3.4.1 Load and Store Instructions
3.4.2 Arithmetic Instructions
3.4.3 Logical Instructions
3.4.4 Register Transfer Instructions
3.4.5 Branch Instructions
3.4.6 Special Instructions
3.4.7 Buffer Selector Instructions
3.5 DATANET Assessment
Chapter Four
4.1 DN-30 Operation
4.2 GE-235 Operation
4.3 System Software
4.3.1 Concept of Operations
4.3.2 DN-30 Executive
4.3.2.1 Scheduling
4.3.2.2 Job Priority Levels
4.3.3 GE-235 Executive
4.3.3 Catalogs
4.3.4 Editor
4.4 GE-265 Assessment
Chapter Five
5.1 GE-312
5.1.1 Applications of the GE-312
5.1.2 Brief Overview of the GE-312
5.2 GE-412
5.2.1 GE-412 System Architecture
5.2.2. Central Processor Architecture
5.2.2.1 Arithmetic Registers
5.2.2.2 Control Registers
5.2.2.3 Address Modification
5.2.2.4 Real-time Clock
5.2.2.5 Automatic Program Interrupts
5.2.2.6 Variable Timing Control for Programs
5.2.2.7 Operator Console
5.2.3 Program and Maintenance Console
5.2.4 Main Memory
5.2.5 Magnetic Drum Storage
5.2.6 Peripheral Equipment
5.2.6.1 Scanner-Distributor
5.2.6.2 Fast Digital Scanner
5.2.6.3 Digital Data Accumulator
5.2.6.4 Digital-to-Analog Converter
5.3 Software Development Aids
5.3.1 General Assembly Program
5.3.2 The General Compiler
5.4 GE-312/412 Instruction Set
5.4.1 Data Transfer and Arithmetic Instructions
5.4.2 Register Manipulation Instructions
5.4.3 Logical Instructions
5.4.4 Shift Instructions
5.4.5 Unconditional branch Instructions
5.4.6 conditional branch Instructions
5.4.7 Automatic Address Modification Instruction
5.4.8 Real-Time Instructions
5.4.9 Magnetic Drum Transfer Instructions
5.4.10 Automatic Program Interrupt Instructions
5.4.11 Miscellaneous Instructions
5.4.12 Unit Record Peripheral I/O Instructions
5.4.13 Other Peripherals Instructions
5.5 GE-412 System Software
5.6 GE-412 Assessment
Chapter Six
6.1 GE-400 Series System Architecture
6.1.1 GE-435 Central Processor
6.1.2 The Processor Channel
6.1.2.1 Processor Status Control Word
6.1.2.2 Program Interrupt Words
6.1.3 Memory
6.1.4 I/O Control Section
6.1.4.1 Executing Control Functions
6.1.5 Direct Access Package
6.1.6 1401 Emulator
6.2 System Console and Peripherals
6.3 GE-4xx Instruction Set
6.3.1 Single Addresses
6.3.2 Two Addresses
6.3.3 Data Movement
6.3.4 Shift Instructions
6.3.3 Arithmetic Instructions
6.3.4 Compare Instructions
6.3.5 Branch Instructions
6.3.6 Logic Instructions
6.3.7 Fixed Index Word Instructions
6.3.8 Accumulator Instructions
6.3.9 Special Purpose Instructions
6.3.10 Peripheral Instructions
6.4 GE-400 Peripherals
6.4.1 CR-20 Card Reader
6.4.2 CP-10 Card Punch
6.4.3 PR-20 Printer
6.4.4 Magnetic Tape Subsystems
6.4.5 TS-20 Perforated Tape Reader/Punch
6.4.6 DS-20 Disc Storage Subsystem
6.4.6.1 DSU Controller
6.4.6.2 Electronics and File Units
6.4.6.3 Programming the DS-20
6.4.6.4 Status Data
6.4.7 MR-20 Magnetic Record Reader/Sorter
6.4.8 Data Communications Units
6.5 GE-400 Time-sharing System
6.6 GE-400 Series Software
6.6.1 Magnetic Tape Processing System
6.6.2 Disc Processing System
6.6.3 Direct Access Processing System
6.6.4 Macro Assembly Program
6.6.4.1 Instruction Format
6.6.4.2 Assembler Phase I
6.7 GE-400 Series Assessment
Chapter Seven
7.1 The GE-600 Genesis
7.2 GE-600 System Architecture
7.2.1 Memory Module
7.2.2 Processor Module
7.2.2.1 Registers
7.2.2.2 Processor Indicators
7.2.2.3 Operation Overlapping
7.2.2.4 Memory Protection
7.2.2.5 Interrupt Procedure
7.2.3 I/O Control Module
7.2.3.1 Micro-Program Generator
7.2.3.2 I/O Processor (IOP)
7.2.4 Peripheral Subsystems
7.3 GE-615
7.4 GE-625
7.5 GE-600 Assessment
Chapter Eight
8.1 GE-635 System Architecture
8.1.1 Instruction Fetching
8.1.2 Memory Protection
8.1.3 Master Mode Operation
8.1.4 Interrupt Execution
8.1.5 Multiple Adders
8.1.6 Faults
8.1.6.1 Instruction-Generated Faults
8.1.6.2 Program-Generated Faults
8.1.6.3 Hardware-Generated Faults
8.1.6.4 Manually-Generated Faults
8.1.7 Interval Timer
8.2 Instruction Set Architecture
8.2.1 Address Modification
8.2.2 Data Movement Instructions
8.2.3 Shifting Instructions
8.2.4 Fixed Point Arithmetic Instructions
8.2.5 Boolean Instructions
8.2.6 Comparison Instructions
8.2.7 Floating Point Load and Store
8.2.8 Floating Point Arithmetic Operations
8.2.9 Transfer of Control
8.2.10 Miscellaneous Operations
8.2.11 Special Operations
8.2.12 Master Mode Operations
8.3 I/O Controller
8.4 Peripheral Equipment Subsystems
8.5 GE-600 Series Assessment
Chapter Nine
9.1 Design Concepts
9.2 System Summary
9.3 System Controller Module
9.3.1 Core Storage
9.3.2 Connect Signals
9.3.3 Interrupt Cells
9.3.4 System Clock
9.4 Processor Modules
9.4.1 Processor Features
9.4.2 Operating Modes
9.4.3 Processor Registers
9.2.3 GIOC Module
9.2.4 Extended Memory Module
9.5 Instruction Set
9.5.1 Address Modification
9.5.2 New Instructions
9.6 GE-645 Enhancements
9.6.1. I/O System
9.6.2 Segmentation and Paging
9.6.3 Segmentation
9.6.4 Descriptors
9.6.5 Base Registers
9.6.6 Indirect Transfer to Segments
9.6.7 Shared Segments
9.6.8 Paging
9.6.9 The Segment Descriptor Word
9.6.10 Paged Descriptor Segment
9.6.11 Associative Memory
9.7 New Mode of Procedure Execution
9.8 System Console
9.9 Generalized I/O Controller
9.9.1 GIOC Mailboxes
9.9.2 GIOC Control Words
9.9.3 Channels
9.9.4 Data Channels
9.9.5 List Channels
9.9.6 Connect Channel
9.9.7 Status Channels
9.9.8 Adapters
9.9.9 Status Events
9.9.10 Initializing Data Channel Operation
9.10 System Configuration Console
9.11 Peripheral Equipment
9.11.1 Disc Storage Subsystem
9.11.2 Magnetic Drum Storage System
9.11.3 Mass Storage Subsystem
9.11.4 Magnetic Tape Subsystem
9.11.5 Peripheral Switch Console
9.11.6 Terminal Equipment
9.12 The Multics Operating System
9.13 GE-655
Chapter Ten
10.1 User Interaction
10.2 DTSS Structure
10.3 The End of the First Generation
10.4 The Second Generation
10.5 DTSS Assessment
Chapter Eleven
11.1 The Goals for BASIC
11.2 The Basics of BASIC
11.2.1 The First Dartmouth Version
11.2.2 Further Versions of BASIC
11.3 The Mark II/III Basic Language
11.3.1 A Complete BASIC Program
11.3.2 Essential BASIC Statements
11.3.3 Enhanced BASIC Statements
11.4 The Success of BASIC
11.5 Assessment of BASIC
Chapter Twelve
12.1 GECOS Structure
12.1.1 Input Media Conversion
12.1.2 Allocation
12.1.3 Monitor
12.1.4 Termination
12.1.5 Output Media Conversion
12.1.6 Roadblock AND FORCED RELINQUISH
12.1.7 Dispatcher
12.2 GEMME
12.2.1 GEMME Calls
12.2.2 Requests For Service
12.2.3 Multiprogramming
12.3 General I/O Supervisor
12.3.1 GEINOS
12.3.1.1 Data Control Word
12.3.1.2 GEINOS Device Commands
12.3.1.3 Return Status
12.3.2 I/O Operation Execution
12.3.2.1 GESYOT
12.3.2.2 GEEPR
12.3.2.3 GEFALT
12.4 GEFLOW
12.5 General File Record Control
12.6 General Loader
12.6.1 Overlays
12.7 General Remote Terminal Supervisor
12.8 GECOS Control Cards
12.9 GECOS Assessment
Chapter Thirteen
13.1 GEM
13.1.1 Symbol Types
13.1.2 Expressions
13.1.3 Address Modification
13.1.4 Pseudo-Operations
13.1.4.1 Control Pseudo-operations
13.1.4.2 Location Counter Pseudo-operations
13.1.4.3 Symbol-Defining Pseudo-operations
13.1.4.4 Data Generating Pseudo-operations
13.1.4.5 Storage Allocation Pseudo-operations
13.1.4.6 Conditional Pseudo-operations
13.1.4.7 Special Word Pseudo-operations
13.1.4.8 Tally Pseudo-operations
13.1.4.9 Repeat Pseudo-operations
13.2 Integrated Data Store
13.2.1 IDS Requirements
13.2.2 Data Organization
13.2.3 Data and Procedural Language
13.2.3.1 Procedural Commands
13.2.3.2 IDS Retrieval Rules
13.2.4 I/O Controller
13.3 IDS Assessment
Chapter Fourteen
14.1 Accessing the Service
14.1.1 Signing On
14.1.2 Entering a Program
14.1.3 Signing Off
14.2 Data Files
14.3 Program Libraries
14.4 System Communication
14.5 Time-sharing Applications
Chapter Fifteen
Ezercises for the Reader
Glossary
References
Index

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Mainframe Computer Systems

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