Pipelined Multiprocessor System-on-Chip for Multimedia
1st Edition
Published on 26. November 2013
VIII, 169 pages
978-3-319-01113-4 (ISBN)
Description
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
More details
Series
Language
English
Place of publication
Cham
Switzerland
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Product notice
Reflowable
Illustrations
VIII, 169 p. 40 illus., 32 illus. in color.
File size
5,20 MB
ISBN-13
978-3-319-01113-4 (9783319011134)
DOI
10.1007/978-3-319-01113-4
Schweitzer Classification
Other editions
Additional editions
Haris Javaid | Sri Parameswaran
Pipelined Multiprocessor System-on-Chip for Multimedia
Analyses and Optimizations
Book
12/2013
1st Edition
Springer
€106.99
Shipment within 10-15 days
Content
Introduction.- Literature Survey.- Optimisation Framework.- Performance Estimation of Pipelined MPSoCs.- Design Space Exploration of Pipelined MPSoCs.- Adaptive Pipelined MPSoCs.- Power Management in Adaptive Pipelined MPSocs.- Multi-mode Pipelined MPSoCs.- Conclusions and Future Work.
