Advanced Techniques for Optimal Sizing of Analog Integrated Circuits
Description
A novel and authoritative approach to quantum machine learning in integrated circuits design optimization
In Advanced Techniques for Optimal Sizing of Analog Integrated Circuits, a team of distinguished researchers deliver a comprehensive discussion of the theory, models, methodologies, practical implementation, and utilization of integrated circuit (IC) design. The authors explain IC design optimization, demonstrating cost-effective and time-saving design approaches, as well as techniques likely to be impactful in the near future.
The book covers major topics in the field, describing key concepts, recent advances, effective algorithms, and pressing challenges associated with analog circuit sizing optimization. It discusses using both animal and human-inspired optimization algorithms to create basic and quantum machine learning methods.
Readers will also find:
- A novel approach to quantum machine learning in integrated circuit design optimization
- A range of introductory and advanced topics suitable for students, advanced professionals, and researchers
- Detailed illustrations that clarify abstract, complicated engineering concepts
- Complete treatments of animal behavior-inspired optimization algorithms, including particle swarm optimization, firefly algorithm, cuckoo search, and bat algorithm
Perfect for researchers in engineering, computer scientists, professors, and senior undergraduate and graduate students in integrated circuit design, this book will also benefit students of machine learning, computer science, quantum computing, and optimization.
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Persons
Trang Hoang is an Associate Professor at Ho Chi Minh City University of Technology, Vietnam National University in Ho Chi Minh City, Vietnam.
Thinh Quang Do is a Research Assistant and a PhD student at the Memorial University of Newfoundland, Canada.
Thang Quoc Nguyen is a Research Assistant and a PhD student at the Memorial University of Newfoundland, Canada.
Hoang Trong Nguyen is a Research Assistant and a Master student at the Memorial University of Newfoundland, Canada.
Lihong Zhang is a Full Professor with the Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science at the Memorial University of Newfoundland, Canada.
Octavia A. Dobre is a Professor and the Tier-1 Canada Research Chair at Memorial University of Newfoundland, Canada.
Trung Q. Duong is the Canada Excellence Research Chair and a Full Professor at the Memorial University of Newfoundland, Canada. He is also an Adjunct Professor at Queen's University Belfast, UK and a Visiting Professor at Kyung Hee University, South Korea.
Content
About the Authors xi
Preface xiii
Acronyms xvii
1 Overview and Problem Formulation 1
1.1 Integrated Circuit Design Optimization 1
1.2 The Need for Analog IC Design Optimization 2
1.3 Analog Circuit Sizing Procedure 4
1.3.1 Topology Selection 5
1.3.2 Parameter Selection for Optimization 5
1.3.3 Optimization Design Variables 5
1.3.4 Objective Function and Design Constraints 6
1.4 Problem Modeling for Analog Circuit Sizing Optimization 6
1.4.1 Problem Modeling for Analog Circuit Sizing Optimization 6
1.4.2 Criteria for Optimization Assessment 8
1.4.3 Correlation Between Optimization Algorithms and Analog Circuit Sizing 9
References 9
2 Evolutionary Algorithms in Analog Circuit Sizing Optimization 11
2.1 Genetic Algorithm 11
2.1.1 Population Initialization 13
2.1.2 Decoding 13
2.1.3 Fitness Evaluation 13
2.1.4 Selection 14
2.1.5 Crossover 14
2.1.6 Mutation 15
2.2 Self-Adaptive Differential Evolution 15
2.2.1 Population Initialization and Fitness Evaluation 16
2.2.2 Mutation 17
2.2.3 Crossover 17
2.2.4 Selection 17
2.3 Biogeography-Based Optimization 18
2.3.1 Biogeography: The Science of Evolution 18
2.3.2 Biogeography and Optimization 21
2.3.2.1 Migration 21
2.3.2.2 Mutation 21
2.4 Case Study: Single-Tail Dynamic Comparator 22
2.4.1 Proposed Python-Spectre Model to Optimize Delay and Power of the Dynamic Comparator 23
2.4.2 Results and Discussion 26
References 29
3 Animal-Behavior-Inspired Algorithms in Analog Circuit Sizing Optimization 33
3.1 Particle Swarm Optimization 33
3.2 Firefly Algorithm 36
3.2.1 Algorithm Formulation 37
3.2.2 Implementation 39
3.3 Cuckoo Search 41
3.4 Bat Algorithm 43
3.5 Flower Pollination Algorithm 45
3.5.1 Global Pollination 47
3.5.2 Local Pollination 48
3.5.3 Elitist Selection 48
3.6 Ant Colony Optimization 49
3.7 Case Study: PSO and Cuckoo Search Algorithm Implementation in Band-gap Reference Circuit Design 51
References 53
4 Human-Behavior-Inspired Algorithms in Analog Circuit Sizing Optimization 57
4.1 Ali Baba and the Forty Thieves Algorithm 57
4.1.1 Basic AFT Algorithm 57
4.1.2 Self-Adaptive AFT (SaAFT) 60
4.2 Drawer Algorithm 62
4.3 Political Optimizer 65
4.3.1 Party Formation and Constituency Allocation 68
4.3.2 Election Campaign 69
4.3.3 Party Switching 70
4.3.4 Parliamentary Affairs 72
4.4 War Strategy Optimization 72
4.4.1 Attack Strategy 74
4.4.2 Rank and Weight Update 75
4.4.3 Defense Strategy 76
4.4.4 Replacement of Weak Soldiers 76
4.5 Case Study: Two-Stage Miller-Compensated Operational Amplifier with SaAFT and PO 76
4.5.1 Choice of the Objective Function 77
4.5.2 Initialization Steps for Optimization 77
4.5.3 Results and Discussion 79
References 83
5 Machine Learning in Analog Circuit Sizing Optimization 85
5.1 Machine Learning Overview 85
5.1.1 Machine Learning: A Heuristic Sandbox 85
5.1.2 Procedure of Applying Machine Learning 87
5.1.3 Supervised Learning 89
5.1.4 Unsupervised Learning 90
5.1.5 Reinforcement Learning 92
5.2 Neural Networks 94
5.3 Hyperparameter Search 96
5.4 Deep Reinforcement Learning 97
5.5 Case Study: High-Level Design of Delta-Sigma Analog-to-Digital Converter 99
5.5.1 Delta-Sigma ADC: Topology and Sizing 99
5.5.2 Multi-agent Proximal Policy Optimization 100
5.5.3 Results and Discussion 101
References 104
6 Quantum Mechanics and Analog Circuit Sizing Optimization 105
6.1 Quantum Computing 105
6.1.1 Quantum States 106
6.1.2 The Bloch Sphere 107
6.1.3 Quantum Gates 107
6.1.3.1 Hadamard Gate 107
6.1.3.2 Rotation Gate 108
6.1.3.3 Pauli Gates 109
6.1.4 Hadamard Product 109
6.1.5 Frobenius Norm 109
6.2 Quantum Variational Optimization 110
6.2.1 Initialize the System 110
6.2.1.1 Method 1. Amplitude Embedding 110
6.2.1.2 Method 2. Angle Encoding 111
6.2.1.3 Method 3. Reference State Construction 112
6.2.2 Prepare an Ansatz 112
6.2.2.1 Parameterized Quantum Operator 112
6.2.2.2 Heuristic Ansatze and Trade-Offs 113
6.2.2.3 N-Local Circuits 113
6.2.3 Readout 114
6.2.3.1 Method 1. Sampler 115
6.2.3.2 Method 2. Estimator 115
6.2.4 Evaluate Cost Function 116
6.2.5 Optimize Variational Parameters 116
6.3 Grover Optimizer 117
6.3.1 Initialization 118
6.3.2 Oracle Operator 119
6.3.3 Grover Diffusion Operator 122
6.3.4 Grover Iteration 123
6.4 Quantum Annealing 125
6.4.1 Adiabatic Quantum Computing 125
6.4.2 Quantum Annealing 126
6.5 Quantum Inspiration for Classical Algorithms 129
6.5.1 Quantum Population Initialization 130
6.5.2 Measurement 130
6.5.3 Decoding 131
6.5.4 Fitness Evaluation 131
6.5.5 Quantum Rotation 132
6.5.6 Algorithm-Based Quantum Population Update 133
6.5.7 Quantum Genetic Algorithm 133
6.5.7.1 Selection 134
6.5.7.2 Quantum Crossover 134
6.5.7.3 Quantum Mutation 134
6.5.8 Hybrid Quantum Firefly-Genetic Algorithm 135
6.6 Case Study: Auto-Adjusting Hybrid Quantum Genetic Algorithm for Two-Stage Op-Amp Design 136
6.6.1 Initialization Steps for Optimization 136
6.6.2 Results and Discussion 136
References 141
Index 143
1
Overview and Problem Formulation
Circuit sizing is one of the three main phases of analog circuit design, which contributes enormously to the development of integrated circuit (IC) technology. This chapter discusses the importance of circuit sizing as well as the various challenges that designers might face in handling this task. The general procedure and problem formulation for sizing design, which involves multiple constraints and trade-offs, are also presented.
1.1 Integrated Circuit Design Optimization
In recent decades, integrated circuits (ICs) have played an essential role in modern technology as the fundamental building blocks of electronic devices. Consisting of numerous basic elements called transistors that behave as controlled switches, ICs have been able to form almost any kind of functional device that meets users' needs. Based on their material and operation, transistors can have many different forms and names, among which metal-oxide-semiconductor field effect transistor (MOSFET) is the most commonly used. The advent of complementary metal-oxide semiconductor (CMOS) technology, which creates pairs of n-type and p-type MOSFETs in circuit logic, has offered significant improvement to the integrity of ICs, particularly analog ICs, thanks to the ability to cancel noise, reduce static power consumption, and occupy less space. This has paved the way for the revolution of the IC industry, enabling the development of high-quality computers, smartphones, and countless other gadgets that transform the way we live and work. As a result, CMOS technology is viewed as the dominant technology in the field of microelectronics. Sizing, which indicates the direct optimization of the physical sizes of ICs' transistors, has since been thoroughly studied to satisfy the ever-increasing demand of the electronics market and the exponential growth in the number of transistors fabricated on a chip to enhance its density and performance. In fact, as of 2020, the deep learning processor Wafer Scale Engine 2 by Cerebras has 2.6 trillion MOSFETs on the TSMC 7 nm FinFET process. Moreover, the average number of transistors on a single chip nowadays has reached billions. Dealing with this huge number of transistors extends the search space to such a great extent that it poses serious challenges to the scalability and reliability of the circuit design flow [1].
In addition to the enormous search space, turnaround time should be another factor to consider. The increase in chip density resulting from the decrease in the transistor's dimension leads to a remarkably higher level of complexity in both the semiconductor process and design constraints. The growing demand for high-quality ICs to meet modern requirements, such as high accuracy, low latency, and high speed, further intensifies the intricacy and complexity of the design. Electrical design automation (EDA) has been applied in the IC design procedure, where technical simulation and evaluation tools are implemented to automate the process. Consequently, the turnaround time can be shortened considerably, though proper manipulation and algorithms/techniques for EDA may not be available or usable as the scale of these ICs continues to increase. For these very high-scale level ICs, it should take a long time for conventional EDA to obtain an optimal solution. In the worst case, a solution cannot be found and the designers are required to relax their constraints on efficiency. A flaw within the design procedure, which involves many decisive steps, can cause postponement, delay, or low-quality products. Since the turnaround time of a chip is affected by the efficiency of the EDA [2], the growth in the number of transistors per chip may delay time-to-market with undesirable impacts.
To address the aforementioned issues regarding the enormous search space and time to market, there arises the need for more advanced design techniques as support for the available EDA. Artificial intelligence (AI), with its subset machine learning (ML), has been utilized in a variety of areas. Instead of exploring the design search space in a random or unstructured order as traditional methods, AI/ML solutions are oriented based on previous data and reasonable predictions. In other words, AI/ML algorithms can identify data patterns and make relevant decisions accordingly [2]. Furthermore, thanks to the ability to process vast amounts of data simultaneously and explore multiple solutions in a parallel manner, quantum computing has also attracted the attention of both industry and academia. Therefore, AI, ML, and quantum computing should be promising candidates to handle the obstacles in the development of IC design.
1.2 The Need for Analog IC Design Optimization
We are witnessing how wireless communication, thanks to the development of high-speed wireless links such as Bluetooth Low Energy (BLE), Wi-Fi, ZigBee, and LoRa, has reached a level of ubiquity. This is comparable to the state of electrical power distribution, which facilitates seamless connections among various electronic devices, including laptops, cameras, phones, and domestic appliances [3]. This surge in wireless communication can be attributed to several converging factors. Primarily, the continuous advancement in the quantity and quality of electronic circuits and components has played a pivotal role in this development process. In fact, recent advances in CMOS technology have significantly enhanced the integrity of CMOS ICs, mainly analog ICs, which are responsible for processing and transmitting analog signals, especially those in the radio frequency (RF) spectrum. Analog circuits, which process the noisy continuous signals into digitized ones, are usually built upon complex mathematical models to cope with the noise, process variations, nonlinear effects, and parasitic components. As a result, the scale of analog ICs is relatively small, and their automation is somewhat limited due to a large number of variables and computations. Moreover, maintaining integrity enhancement along with the growing demand for high-quality ICs to meet modern communication requirements, such as ultra-high accuracy, ultra-low latency, and ultra-high speed requirements in sixth-generation (6G) network communication [4], is making the design of analog circuits increasingly intricate and complex.
In digital circuit design, the design automation procedure has matured, as can be seen by the development of hardware description languages (HDLs) such as VHDL, Verilog, and SystemVerilog, and the widespread application of Electronic Design Automation (EDA) tools from Cadence, Synopsys, and Siemens. In contrast, analog IC design automation is still an open research area. This disparity between digital and analog design can be explained by the difficulty in abstracting standardization of the analog circuit procedure due to the continuity of the analog signal. In digital circuit design, the signal is a sequence of two logical levels, 0 and 1, and the specifications are functions of two logical levels only. Based on the circuit behavior described in the form of HDL, the EDA tools synthesize the digital circuit in the form of functional blocks, then realize these functional blocks by using the standard cells provided by the manufacturer. In contrast, the continuity of the analog signal leads to the diversity of the specifications of an analog IC, resulting in a broader design space of device size and topology, which the standard cell library cannot cover. Moreover, continuous analog signal metrics are more complex to reach and at lower accuracy than digital signals, which have already been quantized. Therefore, in digital circuit physical design, mathematical equations can be applied to guide the computer on how to do placement and routing to satisfy some constraints, while in analog IC design, a similar concept is hard to apply. Hence, the achievement in analog IC design automation is still limited. Analog IC design is still heavily manual in a time-consuming and labor-intensive design cycle that negatively impacts IC production businesses, causing potential market share losses due to delayed product launches. In fact, as highlighted in [5], IC design businesses can lose up to 14% of market shares if products are introduced four weeks late.
The process of designing analog ICs follows a structured sequence comprising three main phases: topology design, transistor sizing, and physical design (layout). The first phase involves converting the specified design requirements into a circuit structure. This task strongly depends on the designer's expertise in selecting and connecting suitable components such as MOSFETs, resistors, inductors, and capacitors, into a unified circuit that could reach the required specifications. Subsequent to the topology design is the crucial phase of transistor sizing, where the designer meticulously adjusts the width and length of each transistor in the selected architecture. It is worth mentioning that although initial estimates involve mathematical analysis, complex and nonlinear relationships among component parameters and performance metrics often require an iterative method. This is due to the limitations of existing mathematical models in fully capturing the intricate interactions between these elements. Therefore, designers rely on a trial-and-error approach, beginning with calculated size approximations and then refining them through extensive simulations. This iterative procedure includes the...
