Advanced Techniques for Assertion-Based Verification in Hardware Designs Using Data Mining Algorithms
Description
This book introduces leading-edge techniques for verifying the complex electronic systems used in industries such as aerospace, automotive, and medical devices, and ensuring the safety and security of these systems. By focusing on advanced verification and security verification methods, the author addresses the critical need to detect and prevent potential bugs, errors, and vulnerabilities such as Hardware Trojans in embedded systems. With an emphasis on innovative approaches to assertion-based verification, this book provides valuable insights for engineers, researchers, and professionals dedicated to enhancing the functional verification, security, and trustworthiness of critical technological systems.
The methods described in this book address key shortcomings in current automatic assertion miners used for assertion-based verification, such as long execution times, excessive and redundant assertion generation, and inconsistency among generated assertions. The author discusses several innovative methods, tools and techniques, such as ARTmine, IMMizer, and Dominance, which enhance functional verification, and facilitate the automatic generation, evaluation, and minimization of assertions. Additionally, novel techniques are introduced for security verification, including a security-based assertion miner for RISC-V processors and ADAssure for debugging and bug localization in autonomous driving control algorithms of autonomous vehicles.
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Mohammad Reza Heidari Iman is currently a postdoctoral researcher at TIMA Laboratory, Grenoble, France. He earned his PhD from Tallinn University of Technology, Estonia, in August 2024. His research interests include verification and assertion-based verification in safety-critical embedded systems, hardware security, and the application of AI in hardware security and verification. He is a program committee member for conferences such as ETS and IOLTS and also serves as a reviewer for leading journals and conferences, including IEEE TCAD, DATE, ETS, VLSI-SoC, IOLTS, and CODES+ISSS.
Content
Introduction.- Background.- State-of-the-art.- Automatic Generation of Assertions for Functional Verification.- Automatic Evaluation and Minimization of Assertions.- Automatic Generation of Assertions for Security Verification.- Conclusion and Future Directions.
