Power-Aware Testing and Test Strategies for Low Power Devices
1st Edition
Published on 11. March 2010
XXI, 363 pages
978-1-4419-0928-2 (ISBN)
Description
Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.
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Other editions
Additional editions
Patrick Girard | Nicola Nicolici | Xiaoqing Wen
Power-Aware Testing and Test Strategies for Low Power Devices
Book
09/2014
Springer
€117.69
Shipment within 15-20 days
Patrick Girard | Nicola Nicolici | Xiaoqing Wen
Power-Aware Testing and Test Strategies for Low Power Devices
Book
11/2009
Springer
€160.49
Shipment within 15-20 days
Content
Fundamentals of VLSI Testing.- Power Issues During Test.- Low-Power Test Pattern Generation.- Power-Aware Design-for-Test.- Power-Aware Test Data Compression and BIST.- Power-Aware System-Level Test Planning.- Low-Power Design Techniques and Test Implications.- Test Strategies for Multivoltage Designs.- Test Strategies for Gated Clock Designs.- Test of Power Management Structures.- EDA Solution for Power-Aware Design-for-Test.
