
RISC-V Assembly Language Programming using ESP32-C3 and QEMU
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The availability of the Espressif ESP32-C3 chip provides a way to get hands-on experience with RISC-V. The open sourced QEMU emulator adds a 64-bit experience in RISC-V under Linux. These are just two ways for the student and enthusiast alike to explore RISC-V in this book.
The projects in this book are boiled down to the barest essentials to keep the assembly language concepts clear and simple. In this manner you will have "aha!" moments rather than puzzling about something difficult. The focus in this book is about learning how to write RISC-V assembly language code without getting bogged down. As you work your way through this tutorial, you'll build up small demonstration programs to be run and tested. Often the result is some simple printed messages to prove a concept. Once you've mastered these basic concepts, you will be well equipped to apply assembly language in larger projects.
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Content
- RISC-V Assembly Language Programming
- All rights reserved.
- Contents
- 1 Introduction
- 1.1. The Joy of the Machine
- 1.2. Assembler Language
- 1.3. Why RISC-V?
- 1.4. Base Instruction Sets Covered
- 1.5. Projects in this Book
- 1.6. What do you need?
- 1.6.1. ESP32-C3 Hardware
- 1.7. Assumptions About the Reader
- 1.8. Summary
- 2 ESP32-C3 Installation
- 2.1. ESP32-C3 Device
- 2.2. Manual Installation (Linux and MacOS)
- 2.3. Windows Install
- 2.4. Summary
- 3 Installation and Setup of QEMU
- 3.1. Linux/MacOS Platforms
- 3.2. Windows
- 3.3. Installing QEMU on MacOS
- 3.4. Install QEMU on Devuan Linux
- 3.5. QEMU Package Search
- 3.5.1. Building QEMU on Linux
- 3.5.2. Basic Build Steps
- 3.5.3. Linux/MacOS Setup of Fedora Linux
- 3.5.4. Linux/MacOS Boot Fedora Linux
- 3.5.5. Linux/MacOS Boot Test
- 3.6. Installing QEMU on Windows
- 3.7. Summary
- 4 Architecture
- 4.1. Program Counter Register
- 4.2. Endianness
- 4.3. General Purpose Registers
- 4.4. Introducing Subsets
- 4.5. Register Specifics
- 4.5.1. No Flag Bits
- 4.5.2. Register x0 / Zero
- 4.5.3. Register x1 / ra
- 4.5.4. Register x2 / sp
- 4.5.5. Register x3 / gp
- 4.5.6. Register x4 / tp
- 4.5.7. Registers x5-x7 / t0-t2
- 4.5.8. Register x8 / s0 / fp
- 4.5.9. Register x9 / s1
- 4.5.10. Registers x10-x11 / a0-a1
- 4.5.11. Registers x12-x17 / a2-a7
- 4.5.12. Registers x17-x27 / s2-s11
- 4.5.13. Registers x28-x31 / t3-t6
- 4.5.14. Register Summary
- 4.6. Instruction Set Base Subsets/Extensions
- 4.7. ESP32-C3 Hardware
- 4.8. QEMU RISC-V 64 Bit Emulator
- 4.9. RISC-V Privilege Levels
- 4.10. RISC-V is Huge
- 4.11. Summary
- 5 Getting Started
- 5.1. Memory Models & Data Types
- 5.1.1. RV32 Model
- 5.1.2. RV64 Model
- 5.2. The Impact of XLEN
- 5.3. First Exercise
- 5.3.1. The Main Program
- 5.3.2. Assembler Routine add3
- 5.3.3. Assembly Language Format
- 5.3.4. Pseudo Opcode .global
- 5.3.5. Pseudo Opcode .text
- 5.3.6. The add Opcode
- 5.3.7. Calling add3
- 5.3.8. RV64I Consideration
- 5.3.9. Running the Demonstration
- 5.4. First Exercise on ESP32-C3
- 5.5. Assembler Listings
- 5.5.1. ESP32-C3 Assembler Listing
- 5.5.2. Influencing Assembly Code
- 5.5.3. Objdump
- 5.6. Summary
- 6 Load and Store Memory
- 6.1. A Word About Word Sizes
- 6.2. Load Instructions
- 6.3. Load Program Example
- 6.4. The .data Section
- 6.5. Unsigned Values
- 6.6. Memory Alignment
- 6.7. Experiment
- 6.8. Immediate Values
- 6.9. The li Pseudo-Op
- 6.10. The addi Opcode
- 6.11. Pseudo-Op mv
- 6.12. Loads under RV64I
- 6.13. The .section Pseudo-Op
- 6.14. Storing Data
- 6.15. Review
- 6.16. RISC-V Assembler Modifiers
- 6.17. Summary
- 7 Calling Convention
- 7.1. Register Usage
- 7.2. Call Procedure
- 7.2.1. Opcode jal
- 7.2.2. Pseudo Opcode jr
- 7.2.3. Pseudo Opcode ret
- 7.2.4. General Call Procedure
- 7.2.5. Call to 32-bit Absolute Address
- 7.2.6. Revised Call Procedure
- 7.2.7. Concrete Call Example
- 7.2.8. Simple Call Experiment
- 7.2.9. Running in gdb
- 7.3. Argument Passing in Registers
- 7.4. The Stack
- 7.4.1. Prologue
- 7.4.2. Epilogue
- 7.4.3. Floating Point Arguments
- 7.4.4. A Big Call Experiment
- 7.5. Calling printf()
- 7.6. Summary
- 8 Flow Control
- 8.1. Branching Instructions
- 8.1.1. Unconditional Transfers
- 8.1.2. Conditional Branches
- 8.2. Shift Opcodes
- 8.3. ESP32-C3 Project
- 8.3.1. Function c_ones()
- 8.3.2. Main Test Program
- 8.3.3. Assembler Function ones()
- 8.4. Compare and Set
- 8.5. Odd Parity Example
- 8.6. RV64I Odd Parity
- 8.7. Position Independent Code
- 8.8. Summary
- 9 Basic Opcodes
- 9.1. Arithmetic Opcodes
- 9.1.1. add, addi and sub
- 9.1.2. lui
- 9.1.3. auipc
- 9.1.4. RV64 Arithmetic
- 9.2. Logical Opcodes
- 9.3. ESP32-C3 Rotate Left
- 9.4. RV64 Rotate Left
- 9.5. ESP32-C3 Rotate Right
- 9.6. Pseudo Opcodes
- 9.7. Unsigned Multi-precision Arithmetic
- 9.8. Signed Multi-precision Arithmetic
- 9.8.1. Signed Overflow
- 9.9. Summary
- 10 Multiply / Divide
- 10.1. Multiplication Operations
- 10.2. Division Operations
- 10.3. Opcode mul/mulu
- 10.4. Opcode mulhs/mulhu
- 10.5. Optimized Multiply
- 10.6. Unsigned Factorial
- 10.7. Opcode div/divu
- 10.8. Optimized Divide
- 10.9 Division By Zero
- 10.10 Divide Overflow
- 10.11 Safe Division
- 10.12. Greatest Common Divisor
- 10.13. Combinations
- 10.14. Summary
- 11 Addressing, Subscripting and Strings
- 11.1. Testing for Null Pointers
- 11.2. Sizeof Type for Pointers
- 11.3. Matrix Memory Layout
- 11.3.1. Subscript Calculation
- 11.4. Identity Matrix Example
- 11.5. String Functions
- 11.5.1. Function strlen()
- 11.5.2. Function strncpy32()
- 11.5.3. String to Integer Conversion
- 11.5.4. What if there is no Multiply?
- 11.5.5. Integer to String Conversion
- 11.6. Indexed Branching
- 11.7. Summary
- 12 Floating Point
- 12.1. Floating Point Registers
- 12.2. GNU Calling Convention
- 12.3. Floating-Point Control and Status Register (fcsr)
- 12.3.1. Rounding Modes fcsr.frm
- 12.3.2. Accrued Exception Flags fcsr.fflags
- 12.4. NaN Generation and Propagation
- 12.5. Opcodes and Data Formats
- 12.6. Load and Store
- 12.7. Floating Computation
- 12.8. Conversion Operations
- 12.8.1. Floating-Point Zero
- 12.8.2. Conversion Failures
- 12.9. Floating-Point Signs
- 12.10. Floating-Point Move
- 12.11. Floating-Point Compare
- 12.12. Classify Operation
- 12.13. Fahrenheit to Celsius Revisited
- 12.14. Summary
- 13 Portability
- 13.1. C/C++ Pre-Processor
- 13.2. Testing for RISC-V Architecture
- 13.3. Testing For Integer Multiplication
- 13.4. RV32 vs RV64
- 13.5. Assembler Macros
- 13.6. Summary
- 14 Determining Support
- 14.1. Privilege Levels
- 14.1.1. Machine Level
- 14.1.2. Supervisor Level
- 14.1.3. User Level
- 14.2. Control and Status Registers
- 14.2.1. Machine ISA Register
- 14.3. Opcodes
- 14.4. ESP32-C3
- 14.5. Reporting MISA
- 14.6. RV64 Platform
- 14.7. Counters
- 14.7.1 Project rdcycle
- 14.7.2. ESP32-C3 rdcycle Support
- 14.8. Summary
- 15 JTAG Debugging
- 15.1. Espressif JTAG
- 15.2. Device Requirements
- 15.3. Software Components
- 15.4. JTAG With No Serial Window
- 15.4.1. Starting OpenOCD
- 15.4.2. Problems with OpenOCD
- 15.4.3. Terminating OpenOCD
- 15.4.4. Start gdb
- 15.5. Operating gdb
- 15.5.1. Abbreviations
- 15.5.2 GDB Walkthrough
- 15.5.3. Quitting gdb
- 15.6. JTAG With a Serial Window
- 15.6. Miscellaneous
- 15.7. Summary
- 16 Inline Assembly
- 16.1. Keyword Asm
- 16.2. Basic asm Form
- 16.2.1. Keyword volatile
- 16.2.2. Multiple Instructions
- 16.2.3. Behind the Scenes
- 16.3. Extended Asm
- 16.3.1. Assembler Template
- 16.3.2. Output Operands
- 16.3.2.1. Constraint
- 16.3.3. Input Operands
- 16.3.3.1. Clobbers
- 16.4. Bit Multiply
- 16.5. Example asm goto
- 16.6. Register Constraints
- 16.7. Summary
- Index
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The file format PDF always displays a book page identically on any hardware. This makes PDF suitable for complex layouts such as those used in textbooks and reference books (images, tables, columns, footnotes). Unfortunately, on the small screens of e-readers or smartphones, PDFs are rather annoying, requiring too much scrolling.
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