Computer Safety, Reliability, and Security
Description
This book constitutes the refereed proceedings of the 44th International Conference on Computer Safety, Reliability and Security, SAFECOMP 2025, held in Stockholm, Sweden, during September 2025.
The 15 full papers included in these proceedings were carefully reviewed and selected from 79 submissions. They were organized in topical sections as follows: Safety Arguments/Cases; Data Sets and Dependability Properties; Testing and Complex Environments; Methodologies (1) - Safety Design and Risk Assessment; and Methodologies (2) Machine Learning and Large Language.
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Content
.- Safety Arguments/Cases.
.- SmartGSN: An Online Tool to Semi-automatically Manage Assurance Cases.
.- Principled Safety Assurance Arguments.
.- Consensus Building in Level 4 Automated Driving Field Trials through Assurance Cases.
.- Data Sets and Dependability Properties.
.- Creation and use of a representative dataset for Advanced Persistent Threats detection.
.- How Post-Completion Error Leads to Software Faults and Vulnerabilities: Industrial Case Studies.
.- Efficient Injury Risk Assessment for Automated Driving Systems Using Subset Simulation.
.- Testing and Complex Environments.
.- Alignment of SOTIF and Scenario-based Safety Evaluation Framework.
.- Managing capability in software dependability testing through generic test rigs.
.- Improving Out-of-Distribution Detection via Test-Time Augmentation.
.- Methodologies (1) - Safety Design and Risk Assessment.
.- Can C-Based ECC Models Leverage High-Level Synthesis? Evaluating Description Variants for Efficient Circuit.
.- Hot PASTA: Improved Pragmatics for System-Theoretic Process Analysis.
.- ULS: A Unified Likelihood Scale for Cross-Standard Risk Assessment.
.- Methodologies (2) - Machine Learning and Large Language Models.
.- Large Language Models in Code Co-generation for Safe Autonomous Vehicles.
.-Balancing the Risks and Benefits of using Large Language Models to Support Assurance Case Development.
.- Exploring the Potential of LSTM On Emulating Multiple-bit Fault Injection in SRAM-FPGA.
