Verification Techniques for System-Level Design
Published on 27. July 2010
256 pages
978-0-08-055313-9 (ISBN)
Description
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal and "semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
- First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs
- Formal verification of high-level designs (RTL or higher)
- Verification techniques are discussed with associated system-level design methodology
More details
Other editions
Additional editions
Masahiro Fujita | Indradeep Ghosh | Mukul Prasad
Verification Techniques for System-Level Design
Book
12/2007
Morgan Kaufmann
€93.50
Shipment within 15-20 days
Persons
*Spent 15 years at Fujitsu research laboratories.*Research on synthesis and verification of digital systems for more than 25 years*Full professor at VLSI Design and Education Center in the University of TokyoIndradeep Ghosh received the Bachelor of Technology degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur, India, in 1993, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, New Jersey, in 1995 and 1998, respectively.Since 1998 he has been a member of research staff in at Fujitsu Laboratories of America, Sunnyvale, California. He has authored or co-authored more that 40 technical articles in international journals and conferences and holds 6 US patents. He has given numerous presentations in international conferences and workshops. In Fujitsu he has been involved in design verification and testing of industrial systems that are currently in production. His research interests include testing, verification, and validation of hardware and software systems. He is senior member of the IEEE and a member of the ACM.Mukul Prasad:Mukul Prasad received the Bachelor of Technology degree in Electrical Engineering from the Indian Institute of Technology, Delhi, India, in 1995, and the Ph.D. degree in Electrical Engineering & Computer Sciences from the University of California at Berkeley in 2001. Since 2001 he has been a member of the research staff in the Trusted Systems Innovation group at Fujitsu Laboratories of America in Sunnyvale, California. His doctoral thesis and his subsequent research has involved the development and application of verification technologies such as Satisfiability solvers. His work has received a Best Paper Award at the Design Automation & Test in Europe Conference (DATE 2002). His current research addresses various problems in system-level design validation. He has co-authored more than 20 technical papers and presented three tutorials at international conferences and jointly holds 3 U.S. patents in the area of formal validation.
Content
- Front Cover
- Verification Techniques For System-Level Design
- Copyright Page
- Contents
- Acknowledgments
- Chapter 1 Introduction
- Chapter 2 Higher-Level Design Methodology and Associated Verification Problems
- 2.1 Introduction
- 2.2 Issues in High-Level Design
- 2.3 C/C++-Based Design and Specification Languages
- 2.3.1 SpecC Language
- 2.3.2 The Semantics of par Statements
- 2.3.3 Relationship with Simulation Time
- 2.4 System-Level Design Methodology Based on C/C++-Based Design and Specification Languages
- 2.5 Verification Problems in High-Level Designs
- Chapter 3 Basic Technology for Formal Verification
- 3.1 The Boolean Satisfiability Problem
- 3.2 The DPLL Algorithm
- 3.3 Enhancements to Modern SAT Solvers
- 3.4 Capabilities of Modern SAT Solvers
- 3.5 Binary Decision Diagrams
- 3.5.1 Manipulation of BDDs
- 3.5.2 Variants of BDDs
- 3.6 Automatic Test Pattern Generation Engines
- 3.6.1 Single Stuck-at Testing for Combinational Circuits
- 3.6.2 Stuck-at Testing in Sequential Circuits
- 3.7 SAT, BDD, and ATPG Engines for Validation
- 3.8 Theorem-Proving and Decision Procedures
- References
- Chapter 4 Verification Algorithms for FSM Models
- 4.1 Combinational Equivalence Checking
- 4.1.1 Sequential Equivalence Checking as Combinational Equivalence Checking
- 4.1.2 Latch Mapping Problem
- 4.1.3 EC Based on Internal Equivalences
- 4.1.4 Anatomy and Capabilities of Modern CEC Tools
- 4.2 Model Checking
- 4.2.1 Modeling Concurrent Systems
- 4.2.2 Temporal Logics
- 4.2.3 Types of Properties
- 4.2.4 Basic Model-Checking Algorithms
- 4.2.5 Symbolic Model Checking
- 4.3 Semi-Formal Verification Techniques
- 4.3.1 SAT-Based Bounded Model Checking
- 4.3.2 Symbolic Simulation
- 4.3.3 Enhancing Simulation Using Formal Methods
- 4.4 Conclusion
- References
- Chapter 5 Static Checking of Higher-Level Design Descriptions
- 5.1 Program Slicing
- 5.1.1 System Dependence Graph
- 5.1.2 Nodes and Edges
- 5.1.3 Concurrency
- 5.1.4 Synchronization on Concurrent Processes
- 5.2 Checking Method and Its Implying Design Flow
- 5.2.1 Basic Static Description Checking
- 5.2.2 Improvement of Accuracy Using Conditions of Control Nodes
- 5.3 Application of the Checking Methods to HW/SW Partitioning and Optimization
- 5.4 Case Study
- 5.4.1 MPEG2
- 5.4.2 JPEG2000
- 5.4.3 Experimental Results on Static Checking
- References
- Chapter 6 Equivalence Checking on Higher-Level Design Descriptions
- 6.1 Introduction
- 6.2 High-Level Design Flow from the Viewpoint of Equivalence Checking
- 6.3 Symbolic Simulation for Equivalence Checking
- 6.4 Equivalence-Checking Methods Based on the Identification of Differences between two Descriptions
- 6.4.1 Identification of Differences between Two Descriptions
- 6.4.2 Symbolic Simulation Based on Textual Differences
- 6.4.3 Example
- 6.4.4 Experimental Results
- 6.5 Further Improvement on the Use of Differences between Two Descriptions
- 6.5.1 Extension of the Verification Area
- 6.5.2 Symbolic Simulation on SDGs
- 6.5.3 Verification Example
- 6.5.4 Discussion of the Strategy of Extension
- 6.5.5 Experimental Results on the Extension-Based Method
- References
- Chapter 7 Model Checking on Higher-Level Design Descriptions
- 7.1 Introduction
- 7.2 Goal of Synchronization Verification in High-Level Designs
- 7.3 Model Checking and High-Level Design Descriptions
- 7.4 Brief Review of SpecC and Its Semantics for Synchronization Verification
- 7.5 Synchronization Verification Framework
- 7.5.1 From SpecC to Boolean SpecC
- 7.5.2 From Boolean SpecC to Mathematical Representations of Equalities/Inequalities
- 7.5.3 Verification Method
- 7.5.4 Validating the Abstract Counterexample
- 7.5.5 Checking for Race Conditions
- 7.5.6 Renaming Variables
- 7.5.7 Predicate Discovery and Boolean SpecC Refinement
- 7.6 Experimental Results
- References
- Chapter 8 Simulation-Based Verification Techniques for System-Level Designs
- 8.1 Introduction
- 8.2 Simulation Types
- 8.2.1 Event-Driven Simulation
- 8.2.2 Cycle-Based Simulation
- 8.2.3 Specification/Behavior-Level Simulation
- 8.2.4 Mixed-Mode Simulation
- 8.3 High-Level Simulation Tools
- 8.3.1 Static Checking (Linting)
- 8.3.2 Simulators, Waveform Viewers, and Debuggers
- 8.4 Simulation Drawbacks
- 8.5 Coverage Metrics
- 8.5.1 Drawbacks of Coverage Metrics
- 8.6 Test-Bench Automation
- 8.6.1 Transaction Level Modeling
- 8.6.2 Property Specification Languages
- 8.6.3 Test-Bench Automation Frameworks
- 8.6.4 Model-Driven Automatic Test-Bench Generation
- 8.6.5 Automatic Test-Bench Generation from Implementation Design
- 8.7 Tackling Performance Issues
- 8.7.1 Emulation and Hardware Acceleration
- 8.7.2 Using Preverified IPs/Cores and Higher Abstraction Levels
- 8.7.3 Correct by Construction Design
- 8.8 Stopping Criteria
- 8.9 An Example Case Study
- 8.10 Conclusion
- 8.11 Future Directions
- References
- Chapter 9 Conclusion
- Index
- A
- B
- C
- D
- E
- F
- H
- I
- J
- K
- L
- M
- N
- O
- P
- Q
- R
- S
- T
- U
- V
- W
- Z
