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3D Design Styles

Paul D. Franzon

North Carolina State University, 2410 Campus Shore Dr., Raleigh, NC, 27606, USA

1.1 Introduction

3D-IC and interposer technologies have demonstrated their capability to reduce system size and weight, improve performance, reduce power consumption, and even improve cost as compared with baseline 2D integration approaches. Though not a replacement for Moore's law, 3D technologies can provide significant improvements in performance per unit of power and performance per unit of cost. The main purpose of this chapter is to provide an overview of product and design scenarios that uniquely leverage 3D-IC technologies in 3D specific ways.

The structure of this chapter is as follows. First, we do a quick review of the 3D technology set. Then we review the main design drivers for using 3D technologies: (i) miniaturization, (ii) provisioning power effective memory bandwidth, (iii) improving performance/power of logic, and (iv) heterogeneous integration for cost reduction to enable unique system capabilities.

1.2 3D-IC Technology Set

There are several technology components that can be mixed and matched in the 3D technology set. The purpose of this section is not to review these in detail, but to introduce them. Other books in this series focus on the technology.

The main 3D-IC technologies of interest are illustrated together in Figures 1.1-1.4. Interposers (Figure 1.1) are so called because they are placed or posed in between the chip and the main laminate package. Using interposers is often referred to as 2.5D integration. A common way to make interposers is to use silicon processing technologies to create a microscale circuit board. Through-silicon vias (s) are fabricated in a silicon wafer, and multiple metal layers are then fabricated on top. These metal layers can be fabricated with thin film processing, typically giving 3-6 metal layers up to a few micrometers thick, or can be fabricated with integrated circuit back-end-of-line (1) techniques, giving 4-6 thinner but planarized metal layers. The latter approach usually reuses a legacy BEOL process, e.g. from the 65 nm technology node. Micron-scale line width and space can be readily achieved. The interposer is usually thinned to 100 µm. Thus 100 µm long TSVs are used to connect the metal layers to the package underneath. The pitch of the TSVs is also typically around 100 µm. Chips are flipped bumped to the top of the interposer, and the interposer connects them to each other and the outside world. The bump pitch between the chip and the interposer can be relatively tight, down to 25 µm, but the interposer package chip must be at conventional scales, typically in the 150+ µm range. The chips on top of the interposer can be single die or multi-chip stacks themselves.

Figure 1.1 Interposer or 2.5D integration.

Figure 1.2 Redistribution layer.

Figure 1.3 3D-IC chip stacking technology set.

Figure 1.4 3D integration in silicon on insulator technology.

Another interposer technology under active investigation is to use glass as a substrate rather than silicon. Then potentially large panel processing techniques, such as those used to make television screens, can be used, and price reduction achieved.

A related technology is to create interconnect on top of an already finished CMOS wafer and use that to connect to chips and inputs/outputs. This is illustrated in Figure 1.2. Additional thin film wiring layers are processed on top of a completed CMOS wafer to connect the chips in that wafer to chips that are placed on top, together with the chip stack IO. It is referred to as a redistribution layer () as the CMOS wafer IOs are redistributed. Not as many wiring layers are possible as with interposers. One application of RDL technology is to make a chip stack of a larger die, e.g. a memory stack, to a smaller die, e.g. a processor.

An exemplar 3D chip stack, or 3D-IC, is shown in Figure 1.3. This illustrates a three-chip stack, two of which incorporate TSVs. The top two chips illustrated in this stack are mated face to face (). That is, the transistor and wiring layers are directly mated. This mating can be done with solder bumps or with a thermocompression or direct bonding technology. The latter technologies have been demonstrated down to 3 µm pitch and have potential for 1 µm pitch. An example of a copper direct bond interconnect technology can be found in [1]. This permits a very high interconnect density between the two chips. These F2F connections can be leveraged in multiple ways to enable higher-performance and lower power logic stacks.

TSVs can be used to connect the face of one chip, through the back of another to the transistor/wiring layer, or to connect chip stack IO through a chip backside. Thus they can connect a chip face to back (F2B, shown in Figure 1.3 between the bottom two chips) or even back to back (, not shown). TSVs are made using techniques that create very vertical vias through the bulk silicon substrate. They have a lower density than an F2F connection but are important for creating chip stacks. For example, the TSVs shown in Figure 1.3 connect the primary IO and power grounds at the bottom up through the chip stack. The layers with TSVs have to be thinned. The chip stack often includes one unthinned layer for mechanical stability (though this is not a requirement).

A fourth option that is only possible in a silicon on insulator () technology is shown in Figure 1.4. In this approach, fabricated wafers are joined F2F using an oxide-oxide bond. Since the transistors are built on top of an oxide layer, a silicon-selective back etch can be used to remove the silicon part of the SOI substrate while not affecting the transistors and interconnect layers. Simple through-oxide vias can then be used to create vertical connections between what were previously separate chips. An example of this process can be found in [2]. If the first two chips in the stack are fabricated without interconnect, then one gets two directly connectable transistor layers in what would be considered a monolithic 3D technology.

1.3 Why 3D

Table 1.1 presents a summary of potential drivers for 3D integration. The desire for thinner smartphone cameras has resulted in the first mainstream high volume use of 3D technologies. However, such miniaturization can also be used for other image sensors and for smart dust sensors. Provisioning large amounts of power effective memory bandwidth appears to be the next volume application of 3D technologies. In contrast, logic stacking or logic-on-memory stacking has had strong but unrealized potential for improving system performance/power. Finally, 3D offers unique opportunities for heterogeneous integration of different technologies.

Table 1.1 Issues that are potential drivers for 3D integration.

Each of these potential design drivers will be explored in detail in the next four sections.

1.4 Miniaturization

Obviously, 3D stacking technologies using thinned silicon have direct potential to reduce system volume. An early application of TSVs was for providing the IO connections cell phone camera frontside imaging sensor (http://image-sensors-world.blogspot.com/2008/09/toshiba-tsv-reverse-engineered.html; http://www.semicontaiwan.org/en/sites/semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdf). The goal was not to leverage 3D chip stacks - these were single die - but to reduce the overall sensor height, at least when compared with conventional packaging approaches.

More recently Sony has leveraged a copper-copper direct bonding technology to create an image sensor as a...