Designing Network On-Chip Architectures in the Nanoscale Era
1st Edition
Published on 18. December 2010
528 pages
978-1-4398-3711-5 (ISBN)
Description
Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the
More details
Edition
1. Auflage
Language
English
Place of publication
London
United Kingdom
Publishing group
Taylor & Francis Ltd
Target group
Professional and scholarly
Computer engineers and chip designers; researchers in high performance computing and networking.
Illustrations
275 s/w Abbildungen, 28 s/w Tabellen
275 b/w images, 28 tables and 4/11 - Book should be back in Micro - new file
ISBN-13
978-1-4398-3711-5 (9781439837115)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Jose Flich | Davide Bertozzi
Designing Network On-Chip Architectures in the Nanoscale Era
Book
09/2019
1st Edition
Chapman & Hall/CRC
€95.70
Shipment within 15-20 days
Jose Flich | Davide Bertozzi
Designing Network On-Chip Architectures in the Nanoscale Era
Book
12/2010
1st Edition
Chapman & Hall/CRC
€197.50
Shipment within 15-20 days
Persons
Jose Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.
Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.
Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.
Content
NoC Technology. The Industrial Perspective. Upcoming Trends. Appendix. Bibliography.
