
System Synthesis with VHDL
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This book addresses the two most active research areas of design automation today: high-level synthesis and system-level synthesis. In particular, a transformational approach to synthesis from VHDL specifications is described.
System Synthesis with VHDL provides a coherent view of system synthesis which includes the high-level and the system-level synthesis tasks. VHDL is used as a specification language and several issues concerning the use of VHDL for high-level and system-level synthesis are discussed. These include aspects from the compilation of VHDL into an internal design representation to the synthesis of systems specified as interacting VHDL processes.
The book emphasizes the use of a transformational approach to system synthesis. A Petri net based design representation is rigorously defined and used throughout the book as a basic vehicle for illustration of transformations and other design concepts. Iterative improvement heuristics, such as tabu search, simulated annealing and genetic algorithms, are discussed and illustrated as strategies which are used to guide the optimization process in a transformation-based design environment. Advanced topics, including hardware/software partitioning, test synthesis and low power synthesis are discussed from the perspective of a transformational approach to system synthesis.
System Synthesis with VHDL can be used for advanced undergraduate or graduate courses in the area of design automation and, more specifically, of high-level and system-level synthesis. At the same time the book is intended for CAD developers and researchers as well as industrial designers of digital systems who are interested in new algorithms and techniques supporting modern design tools and methodologies.
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