Advanced MOS Device Physics

List of ContributorsPrefaceChapter 1 Approaches to Scaling I. Introduction II. A Review of One-Dimensional MOSFET Drain Current Models III. A Short-Channel MOS Drain Current Model IV. Summary ReferencesChapter 2 Current Trends in MOS Process Integration I. Introduction II. n-Channel MOS Transistors for CMOS or NMOS Technologies III. p-Channel MOS Transistors IV. Well Formation for CMOS V. MOS Device Isolation VI. Merged Bipolar/CMOS BiCMOS Processes VII. Silicon-on-Insulator Technologies ReferencesChapter 3 Hot Carrier Effects I. Introduction II. Channel Electric Field III. Substrate Current Model IV. Ydsat and Isub Dependence on Vg and L V. Gate Current and Lucky Electron Model VI. Thermionic Gate Current Model VII. Hot Carrier Mean Free Path and Temperature VIII. Effect of Non-Maxwellian AssumptionChapter 4 Hot-Carrier-Resistant Structures I. Introduction II. Electric Field Reduction III. Graded Drain Structures IV. Gate-to-Source/Drain Overlap V. Device Processing Variations VI. Circuit Design Considerations VII. Optimization and Trade-Offs ReferencesChapter 5 Low-Temperature CMOS I. Introduction II. Low-Temperature Device Physics III. Material Properties IV. Device Reliability Issues V. Circuit and System Performance ReferencesChapter 6 MOSFET Modeling for Circuit Simulation I. Introduction II. Current-Voltage Characteristics III. Capacitance Characteristics IV. Parasitic Elements V. Parameter Extraction VI. Summary Appendix A Appendix B ReferencesChapter 7 Latchup I. Introduction II. Latchup Fundamentals III. Practical Methods of Circuit Evaluation IV. Latchup Prevention Techniques ReferencesChapter 8 Quantum Mechanical and Nonstationary Transport Phenomena in Nanostructured Silicon Inversion Layers I. Introduction II. Semiclassical Conductivity of Quantum MOS Devices III. Quasi-One-Dimensional MOSFETS IV. Surface Superlattice Transistors V. Dynamics of Electron Transport in High Electric Fields ReferencesIndex